2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <timestamp.h>
28 #ifndef CONFIG_IDENT_STRING
29 #define CONFIG_IDENT_STRING ""
32 /* last three long word reserved for cache status */
33 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
34 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
35 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
41 move.w #0x2700,%sr; /* disable intrs */ \
42 subl #60,%sp; /* space for 15 regs */ \
43 moveml %d0-%d7/%a0-%a6,%sp@;
46 moveml %sp@,%d0-%d7/%a0-%a6; \
47 addl #60,%sp; /* space for 15 regs */ \
50 #if defined(CONFIG_CF_SBF)
51 #define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
52 #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
58 * Vector table. This is used for initial platform startup.
59 * These vectors are to catch any un-intended traps.
62 #if defined(CONFIG_CF_SBF)
64 INITSP: .long 0 /* Initial SP */
65 INITPC: .long ASM_DRAMINIT /* Initial PC */
69 INITSP: .long 0 /* Initial SP */
70 INITPC: .long _START /* Initial PC */
74 vector02: .long _FAULT /* Access Error */
75 vector03: .long _FAULT /* Address Error */
76 vector04: .long _FAULT /* Illegal Instruction */
77 vector05: .long _FAULT /* Reserved */
78 vector06: .long _FAULT /* Reserved */
79 vector07: .long _FAULT /* Reserved */
80 vector08: .long _FAULT /* Privilege Violation */
81 vector09: .long _FAULT /* Trace */
82 vector0A: .long _FAULT /* Unimplemented A-Line */
83 vector0B: .long _FAULT /* Unimplemented F-Line */
84 vector0C: .long _FAULT /* Debug Interrupt */
85 vector0D: .long _FAULT /* Reserved */
86 vector0E: .long _FAULT /* Format Error */
87 vector0F: .long _FAULT /* Unitialized Int. */
91 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93 vector18: .long _FAULT /* Spurious Interrupt */
94 vector19: .long _FAULT /* Autovector Level 1 */
95 vector1A: .long _FAULT /* Autovector Level 2 */
96 vector1B: .long _FAULT /* Autovector Level 3 */
97 vector1C: .long _FAULT /* Autovector Level 4 */
98 vector1D: .long _FAULT /* Autovector Level 5 */
99 vector1E: .long _FAULT /* Autovector Level 6 */
100 vector1F: .long _FAULT /* Autovector Level 7 */
102 #if !defined(CONFIG_CF_SBF)
106 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
115 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
116 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
117 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
119 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
120 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
121 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
122 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
125 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
126 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
127 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
128 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
129 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
130 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
131 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
132 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
135 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
136 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
137 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
138 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
139 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
140 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
141 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
142 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
145 #if defined(CONFIG_CF_SBF)
146 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
148 .long 0x00000000 /* checksum, not yet implemented */
149 .long 0x00030000 /* image length */
150 .long TEXT_BASE /* image to be relocated at */
155 move.w #0x2700,%sr /* Mask off Interrupt */
157 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
160 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
163 /* initialize general use internal ram */
165 move.l #(CACR_STATUS), %a1 /* CACR */
166 move.l #(ICACHE_STATUS), %a2 /* icache */
167 move.l #(DCACHE_STATUS), %a3 /* dcache */
172 /* invalidate and disable cache */
173 move.l #0x01004100, %d0 /* Invalidate cache cmd */
174 movec %d0, %CACR /* Invalidate cache */
181 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
184 /* Must disable global address */
185 move.l #0xFC008000, %a1
186 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
187 move.l #0xFC008008, %a1
188 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
189 move.l #0xFC008004, %a1
190 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
192 /* Dram Initialization a1, a2, and d0 */
194 move.l #0xFC0A4074, %a1
195 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
198 /* SDRAM Chip 0 and 1 */
199 move.l #0xFC0B8110, %a1
200 move.l #0xFC0B8114, %a2
202 /* calculate the size */
204 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
205 #ifdef CONFIG_SYS_SDRAM_BASE1
215 /* SDRAM Chip 0 and 1 */
216 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
218 #ifdef CONFIG_SYS_SDRAM_BASE1
219 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
224 /* dram cfg1 and cfg2 */
225 move.l #0xFC0B8008, %a1
226 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
228 move.l #0xFC0B800C, %a2
229 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
232 move.l #0xFC0B8000, %a1 /* Mode */
233 move.l #0xFC0B8004, %a2 /* Ctrl */
236 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
239 #ifdef CONFIG_M54455EVB
241 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
243 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
251 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
254 /* Perform two refresh cycles */
255 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
261 #ifdef CONFIG_M54455EVB
262 move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
264 #elif defined(CONFIG_M54451EVB)
266 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
268 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
274 move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
275 and.l #0x7FFFFFFF, %d1
276 #ifdef CONFIG_M54455EVB
277 or.l #0x10000C00, %d1
278 #elif defined(CONFIG_M54451EVB)
279 or.l #0x10000C00, %d1
288 * DSPI Initialization
289 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
295 /* Enable pins for DSPI mode - chip-selects are enabled later */
297 move.l #0xFC0A4063, %a0
300 /* Configure DSPI module */
301 move.l #0xFC05C000, %a0
302 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
304 move.l #0xFC05C00C, %a0
305 move.l #0x3E000011, (%a0)
307 move.l #0xFC05C034, %a2 /* dtfr */
308 move.l #0xFC05C03B, %a3 /* drfr */
310 move.l #(ASM_SBF_IMG_HDR + 4), %a1
314 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
315 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
317 move.l #0xFC05C02C, %a1 /* dspi status */
319 /* Issue commands and address */
320 move.l #0x8002000B, %d2 /* Fast Read Cmd */
321 jsr asm_dspi_wr_status
322 jsr asm_dspi_rd_status
324 move.l #0x80020000, %d2 /* Address byte 2 */
325 jsr asm_dspi_wr_status
326 jsr asm_dspi_rd_status
328 move.l #0x80020000, %d2 /* Address byte 1 */
329 jsr asm_dspi_wr_status
330 jsr asm_dspi_rd_status
332 move.l #0x80020000, %d2 /* Address byte 0 */
333 jsr asm_dspi_wr_status
334 jsr asm_dspi_rd_status
336 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
337 jsr asm_dspi_wr_status
338 jsr asm_dspi_rd_status
340 /* Transfer serial boot header to sram */
342 move.l #0x80020000, %d2
343 jsr asm_dspi_wr_status
344 jsr asm_dspi_rd_status
346 move.b %d1, (%a0) /* read, copy to dst */
348 add.l #1, %a0 /* inc dst by 1 */
349 sub.l #1, %d4 /* dec cnt by 1 */
350 bne asm_dspi_rd_loop1
352 /* Transfer u-boot from serial flash to memory */
354 move.l #0x80020000, %d2
355 jsr asm_dspi_wr_status
356 jsr asm_dspi_rd_status
358 move.b %d1, (%a4) /* read, copy to dst */
360 add.l #1, %a4 /* inc dst by 1 */
361 sub.l #1, %d5 /* dec cnt by 1 */
362 bne asm_dspi_rd_loop2
364 move.l #0x00020000, %d2 /* Terminate */
365 jsr asm_dspi_wr_status
366 jsr asm_dspi_rd_status
368 /* jump to memory and execute */
369 move.l #(TEXT_BASE + 0x400), %a0
373 move.l (%a1), %d0 /* status */
374 and.l #0x0000F000, %d0
375 cmp.l #0x00003000, %d0
376 bgt asm_dspi_wr_status
382 move.l (%a1), %d0 /* status */
383 and.l #0x000000F0, %d0
386 beq asm_dspi_rd_status
396 #endif /* CONFIG_CF_SBF */
402 #if !defined(CONFIG_CF_SBF)
405 move.w #0x2700,%sr /* Mask off Interrupt */
407 /* Set vector base register at the beginning of the Flash */
408 move.l #CONFIG_SYS_FLASH_BASE, %d0
411 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
414 /* initialize general use internal ram */
416 move.l #(CACR_STATUS), %a1 /* CACR */
417 move.l #(ICACHE_STATUS), %a2 /* icache */
418 move.l #(DCACHE_STATUS), %a3 /* dcache */
423 /* invalidate and disable cache */
424 move.l #0x01004100, %d0 /* Invalidate cache cmd */
425 movec %d0, %CACR /* Invalidate cache */
432 /* set stackpointer to end of internal ram to get some stackspace for
434 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
438 move.l #__got_start, %a5 /* put relocation table address to a5 */
440 bsr cpu_init_f /* run low-level CPU init code (from flash) */
441 bsr board_init_f /* run low-level board init code (from flash) */
443 /* board_init_f() does not return */
445 /*------------------------------------------------------------------------------*/
448 * void relocate_code (addr_sp, gd, addr_moni)
450 * This "function" does not return, instead it continues in RAM
451 * after relocating the monitor code.
455 * r5 = length in bytes
461 move.l 8(%a6), %sp /* set new stack pointer */
463 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
464 move.l 16(%a6), %a0 /* Save copy of Destination Address */
466 move.l #CONFIG_SYS_MONITOR_BASE, %a1
467 move.l #__init_end, %a2
470 /* copy the code to RAM */
472 move.l (%a1)+, (%a3)+
477 * We are done. Do not return, instead branch to second part of board
478 * initialization, now running from RAM.
481 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
488 * Now clear BSS segment
491 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
493 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
500 * fix got table in RAM
503 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
504 move.l %a1,%a5 /* * fix got pointer register a5 */
507 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
517 /* calculate relative jump to board_init_r in ram */
519 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
521 /* set parameters for board_init_r */
522 move.l %a0,-(%sp) /* dest_addr */
523 move.l %d0,-(%sp) /* gd */
526 /*------------------------------------------------------------------------------*/
548 /*------------------------------------------------------------------------------*/
549 /* cache functions */
552 move.l #(CACR_STATUS), %a1 /* read CACR Status */
555 move.l #0x00040100, %d0 /* Invalidate icache */
558 move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup icache */
561 move.l #0x04088020, %d0 /* Enable bcache and icache */
564 move.l #(ICACHE_STATUS), %a1
569 .globl icache_disable
571 move.l #(CACR_STATUS), %a1 /* read CACR Status */
574 move.l #0xFFF77BFF, %d0
575 or.l #0x00040100, %d0 /* Setup cache mask */
576 movec %d0, %CACR /* Invalidate icache */
581 move.l #(ICACHE_STATUS), %a1
588 move.l #(ICACHE_STATUS), %a1
592 .globl icache_invalid
594 move.l #(CACR_STATUS), %a1 /* read CACR Status */
597 move.l #0x00040100, %d0 /* Invalidate icache */
598 movec %d0, %CACR /* Enable and invalidate cache */
603 move.l #(CACR_STATUS), %a1 /* read CACR Status */
606 move.l #0x01040100, %d0
607 movec %d0, %CACR /* Invalidate dcache */
609 move.l #0x80088020, %d0 /* Enable bcache and icache */
612 move.l #(DCACHE_STATUS), %a1
617 .globl dcache_disable
619 move.l #(CACR_STATUS), %a1 /* read CACR Status */
622 and.l #0x7FFFFFFF, %d0
623 or.l #0x01000000, %d0 /* Setup cache mask */
624 movec %d0, %CACR /* Disable dcache */
629 move.l #(DCACHE_STATUS), %a1
634 .globl dcache_invalid
636 move.l #(CACR_STATUS), %a1 /* read CACR Status */
639 move.l #0x81088020, %d0 /* Setup cache mask */
640 movec %d0, %CACR /* Enable and invalidate cache */
645 move.l #(DCACHE_STATUS), %a1
649 /*------------------------------------------------------------------------------*/
651 .globl version_string
653 .ascii U_BOOT_VERSION
654 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
655 .ascii CONFIG_IDENT_STRING, "\0"