3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
11 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/proc-armv/ptrace.h>
38 extern void reset_cpu(ulong addr);
39 static ulong timer_load_val = 0;
41 /* macro to read the 16 bit timer */
42 static inline ulong READ_TIMER(void)
44 LH7A40X_TIMERS_PTR(timers);
45 lh7a40x_timer_t* timer = &timers->timer1;
47 return (timer->value & 0x0000ffff);
51 /* enable IRQ interrupts */
52 void enable_interrupts (void)
55 __asm__ __volatile__("mrs %0, cpsr\n"
65 * disable IRQ/FIQ interrupts
66 * returns true if interrupts had been enabled before we disabled them
68 int disable_interrupts (void)
70 unsigned long old,temp;
71 __asm__ __volatile__("mrs %0, cpsr\n"
74 : "=r" (old), "=r" (temp)
77 return (old & 0x80) == 0;
80 void enable_interrupts (void)
84 int disable_interrupts (void)
93 panic ("Resetting CPU ...\n");
97 void show_regs (struct pt_regs *regs)
100 const char *processor_modes[] = {
101 "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
102 "UK4_26", "UK5_26", "UK6_26", "UK7_26",
103 "UK8_26", "UK9_26", "UK10_26", "UK11_26",
104 "UK12_26", "UK13_26", "UK14_26", "UK15_26",
105 "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
106 "UK4_32", "UK5_32", "UK6_32", "ABT_32",
107 "UK8_32", "UK9_32", "UK10_32", "UND_32",
108 "UK12_32", "UK13_32", "UK14_32", "SYS_32",
111 flags = condition_codes (regs);
113 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
114 "sp : %08lx ip : %08lx fp : %08lx\n",
115 instruction_pointer (regs),
116 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
117 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
118 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
119 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
120 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
121 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
122 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
123 printf ("Flags: %c%c%c%c",
124 flags & CC_N_BIT ? 'N' : 'n',
125 flags & CC_Z_BIT ? 'Z' : 'z',
126 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
127 printf (" IRQs %s FIQs %s Mode %s%s\n",
128 interrupts_enabled (regs) ? "on" : "off",
129 fast_interrupts_enabled (regs) ? "on" : "off",
130 processor_modes[processor_mode (regs)],
131 thumb_mode (regs) ? " (T)" : "");
134 void do_undefined_instruction (struct pt_regs *pt_regs)
136 printf ("undefined instruction\n");
141 void do_software_interrupt (struct pt_regs *pt_regs)
143 printf ("software interrupt\n");
148 void do_prefetch_abort (struct pt_regs *pt_regs)
150 printf ("prefetch abort\n");
155 void do_data_abort (struct pt_regs *pt_regs)
157 printf ("data abort\n");
162 void do_not_used (struct pt_regs *pt_regs)
164 printf ("not used\n");
169 void do_fiq (struct pt_regs *pt_regs)
171 printf ("fast interrupt request\n");
176 void do_irq (struct pt_regs *pt_regs)
178 printf ("interrupt request\n");
183 static ulong timestamp;
184 static ulong lastdec;
186 int interrupt_init (void)
188 LH7A40X_TIMERS_PTR(timers);
189 lh7a40x_timer_t* timer = &timers->timer1;
191 /* a periodic timer using the 508kHz source */
192 timer->control = (TIMER_PER | TIMER_CLK508K);
194 if (timer_load_val == 0) {
196 * 10ms period with 508.469kHz clock = 5084
198 timer_load_val = CFG_HZ/100;
201 /* load value for 10 ms timeout */
202 lastdec = timer->load = timer_load_val;
204 /* auto load, start timer */
205 timer->control = timer->control | TIMER_EN;
212 * timer without interrupts
215 void reset_timer (void)
217 reset_timer_masked ();
220 ulong get_timer (ulong base)
222 return (get_timer_masked() - base);
225 void set_timer (ulong t)
230 void udelay (unsigned long usec)
249 /* check for rollover during this delay */
251 if ((tmp + tmo) < tmp )
252 reset_timer_masked(); /* timer would roll over */
256 while (get_timer_masked () < tmo);
259 void reset_timer_masked (void)
262 lastdec = READ_TIMER();
266 ulong get_timer_masked (void)
268 ulong now = READ_TIMER();
270 if (lastdec >= now) {
272 timestamp += (lastdec - now);
274 /* we have an overflow ... */
275 timestamp += ((lastdec + timer_load_val) - now);
282 void udelay_masked (unsigned long usec)
301 reset_timer_masked ();
303 while (get_timer_masked () < tmo);
307 * This function is derived from PowerPC code (read timebase as long long).
308 * On ARM it just returns the timer value.
310 unsigned long long get_ticks(void)
316 * This function is derived from PowerPC code (timebase clock frequency).
317 * On ARM it returns the number of timer ticks per second.
319 ulong get_tbclk (void)
323 tbclk = timer_load_val * 100;