cpu/i386/sc520.c

   1 /*
   2  * (C) Copyright 2002
   3  * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* stuff specific for the sc520,
  25  * but idependent of implementation */
  26
  27 #include <config.h>
  28
  29 #ifdef CONFIG_SC520
  30
  31 #include <common.h>
  32 #include <config.h>
  33 #include <pci.h>
  34 #include <ssi.h>
  35 #include <asm/io.h>
  36 #include <asm/pci.h>
  37 #include <asm/ic/sc520.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 /*
  42  * utility functions for boards based on the AMD sc520
  43  *
  44  * void write_mmcr_byte(u16 mmcr, u8 data)
  45  * void write_mmcr_word(u16 mmcr, u16 data)
  46  * void write_mmcr_long(u16 mmcr, u32 data)
  47  *
  48  * u8   read_mmcr_byte(u16 mmcr)
  49  * u16  read_mmcr_word(u16 mmcr)
  50  * u32  read_mmcr_long(u16 mmcr)
  51  *
  52  * void init_sc520(void)
  53  * unsigned long init_sc520_dram(void)
  54  * void pci_sc520_init(struct pci_controller *hose)
  55  *
  56  * void reset_timer(void)
  57  * ulong get_timer(ulong base)
  58  * void set_timer(ulong t)
  59  * void udelay(unsigned long usec)
  60  *
  61  */
  62
  63 static u32 mmcr_base= 0xfffef000;
  64
  65 void write_mmcr_byte(u16 mmcr, u8 data)
  66 {
  67         writeb(data, mmcr+mmcr_base);
  68 }
  69
  70 void write_mmcr_word(u16 mmcr, u16 data)
  71 {
  72         writew(data, mmcr+mmcr_base);
  73 }
  74
  75 void write_mmcr_long(u16 mmcr, u32 data)
  76 {
  77         writel(data, mmcr+mmcr_base);
  78 }
  79
  80 u8 read_mmcr_byte(u16 mmcr)
  81 {
  82         return readb(mmcr+mmcr_base);
  83 }
  84
  85 u16 read_mmcr_word(u16 mmcr)
  86 {
  87         return readw(mmcr+mmcr_base);
  88 }
  89
  90 u32 read_mmcr_long(u16 mmcr)
  91 {
  92         return readl(mmcr+mmcr_base);
  93 }
  94
  95
  96 void init_sc520(void)
  97 {
  98         /* Set the UARTxCTL register at it's slower,
  99          * baud clock giving us a 1.8432 MHz reference
 100          */
 101         write_mmcr_byte(SC520_UART1CTL, 7);
 102         write_mmcr_byte(SC520_UART2CTL, 7);
 103
 104         /* first set the timer pin mapping */
 105         write_mmcr_byte(SC520_CLKSEL, 0x72);    /* no clock frequency selected, use 1.1892MHz */
 106
 107         /* enable PCI bus arbitrer */
 108         write_mmcr_byte(SC520_SYSARBCTL,0x02);  /* enable concurrent mode */
 109
 110         write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
 111         write_mmcr_word(SC520_HBCTL,0x04);      /* enable posted-writes */
 112
 113
 114         if (CFG_SC520_HIGH_SPEED) {
 115                 write_mmcr_byte(SC520_CPUCTL, 0x2);     /* set it to 133 MHz and write back */
 116                 gd->cpu_clk = 133000000;
 117                 printf("## CPU Speed set to 133MHz\n");
 118         } else {
 119                 write_mmcr_byte(SC520_CPUCTL, 1);       /* set CPU to 100 MHz and write back cache */
 120                 printf("## CPU Speed set to 100MHz\n");
 121                 gd->cpu_clk = 100000000;
 122         }
 123
 124
 125         /* wait at least one millisecond */
 126         asm("movl       $0x2000,%%ecx\n"
 127             "wait_loop: pushl %%ecx\n"
 128             "popl       %%ecx\n"
 129             "loop wait_loop\n": : : "ecx");
 130
 131         /* turn on the SDRAM write buffer */
 132         write_mmcr_byte(SC520_DBCTL, 0x11);
 133
 134         /* turn on the cache and disable write through */
 135         asm("movl       %%cr0, %%eax\n"
 136             "andl       $0x9fffffff, %%eax\n"
 137             "movl       %%eax, %%cr0\n"  : : : "eax");
 138 }
 139
 140 unsigned long init_sc520_dram(void)
 141 {
 142         bd_t *bd = gd->bd;
 143
 144         u32 dram_present=0;
 145         u32 dram_ctrl;
 146
 147         int val;
 148
 149         int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
 150         int refresh_rate        = CFG_SDRAM_REFRESH_RATE;
 151         int ras_cas_delay       = CFG_SDRAM_RAS_CAS_DELAY;
 152
 153         /* set SDRAM speed here */
 154
 155         refresh_rate/=78;
 156         if (refresh_rate<=1) {
 157                 val = 0;  /* 7.8us */
 158         } else if (refresh_rate==2) {
 159                 val = 1;  /* 15.6us */
 160         } else if (refresh_rate==3 || refresh_rate==4) {
 161                 val = 2;  /* 31.2us */
 162         } else {
 163                 val = 3;  /* 62.4us */
 164         }
 165         write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
 166
 167         val = read_mmcr_byte(SC520_DRCTMCTL);
 168         val &= 0xf0;
 169
 170         if (cas_precharge_delay==3) {
 171                 val |= 0x04;   /* 3T */
 172         } else if (cas_precharge_delay==4) {
 173                 val |= 0x08;   /* 4T */
 174         } else if (cas_precharge_delay>4) {
 175                 val |= 0x0c;
 176         }
 177
 178         if (ras_cas_delay > 3) {
 179                 val |= 2;
 180         } else {
 181                 val |= 1;
 182         }
 183         write_mmcr_byte(SC520_DRCTMCTL, val);
 184
 185
 186         /* We read-back the configuration of the dram
 187          * controller that the assembly code wrote */
 188         dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
 189
 190
 191         bd->bi_dram[0].start = 0;
 192         if (dram_ctrl & 0x80) {
 193                 /* bank 0 enabled */
 194                 dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
 195                 bd->bi_dram[0].size = bd->bi_dram[1].start;
 196
 197         } else {
 198                 bd->bi_dram[0].size = 0;
 199                 bd->bi_dram[1].start = bd->bi_dram[0].start;
 200         }
 201
 202         if (dram_ctrl & 0x8000) {
 203                 /* bank 1 enabled */
 204                 dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
 205                 bd->bi_dram[1].size = bd->bi_dram[2].start -  bd->bi_dram[1].start;
 206         } else {
 207                 bd->bi_dram[1].size = 0;
 208                 bd->bi_dram[2].start = bd->bi_dram[1].start;
 209         }
 210
 211         if (dram_ctrl & 0x800000) {
 212                 /* bank 2 enabled */
 213                 dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
 214                 bd->bi_dram[2].size = bd->bi_dram[3].start -  bd->bi_dram[2].start;
 215         } else {
 216                 bd->bi_dram[2].size = 0;
 217                 bd->bi_dram[3].start = bd->bi_dram[2].start;
 218         }
 219
 220         if (dram_ctrl & 0x80000000) {
 221                 /* bank 3 enabled */
 222                 dram_present  = (dram_ctrl & 0x7f000000) >> 2;
 223                 bd->bi_dram[3].size = dram_present -  bd->bi_dram[3].start;
 224         } else {
 225                 bd->bi_dram[3].size = 0;
 226         }
 227
 228
 229 #if 0
 230         printf("Configured %d bytes of dram\n", dram_present);
 231 #endif
 232         gd->ram_size = dram_present;
 233
 234         return dram_present;
 235 }
 236
 237
 238 #ifdef CONFIG_PCI
 239
 240
 241 static struct {
 242         u8 priority;
 243         u16 level_reg;
 244         u8 level_bit;
 245 } sc520_irq[] = {
 246         { SC520_IRQ0,  SC520_MPICMODE,  0x01 },
 247         { SC520_IRQ1,  SC520_MPICMODE,  0x02 },
 248         { SC520_IRQ2,  SC520_SL1PICMODE, 0x02 },
 249         { SC520_IRQ3,  SC520_MPICMODE,  0x08 },
 250         { SC520_IRQ4,  SC520_MPICMODE,  0x10 },
 251         { SC520_IRQ5,  SC520_MPICMODE,  0x20 },
 252         { SC520_IRQ6,  SC520_MPICMODE,  0x40 },
 253         { SC520_IRQ7,  SC520_MPICMODE,  0x80 },
 254
 255         { SC520_IRQ8,  SC520_SL1PICMODE, 0x01 },
 256         { SC520_IRQ9,  SC520_SL1PICMODE, 0x02 },
 257         { SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
 258         { SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
 259         { SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
 260         { SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
 261         { SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
 262         { SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
 263 };
 264
 265
 266 /* The interrupt used for PCI INTA-INTD  */
 267 int sc520_pci_ints[15] = {
 268         -1, -1, -1, -1, -1, -1, -1, -1,
 269                 -1, -1, -1, -1, -1, -1, -1
 270 };
 271
 272 /* utility function to configure a pci interrupt */
 273 int pci_sc520_set_irq(int pci_pin, int irq)
 274 {
 275         int i;
 276
 277 # if 0
 278         printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
 279 #endif
 280         if (irq < 0 || irq > 15) {
 281                 return -1; /* illegal irq */
 282         }
 283
 284         if (pci_pin < 0 || pci_pin > 15) {
 285                 return -1; /* illegal pci int pin */
 286         }
 287
 288         /* first disable any non-pci interrupt source that use
 289          * this level */
 290         for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
 291                 if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
 292                         continue;
 293                 }
 294                 if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
 295                         write_mmcr_byte(i, SC520_IRQ_DISABLED);
 296                 }
 297         }
 298
 299         /* Set the trigger to level */
 300         write_mmcr_byte(sc520_irq[irq].level_reg,
 301                         read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
 302
 303
 304         if (pci_pin < 4) {
 305                 /* PCI INTA-INTD */
 306                 /* route the interrupt */
 307                 write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
 308
 309
 310         } else {
 311                 /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
 312                 write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
 313
 314                 /* also set the polarity in this case */
 315                 write_mmcr_word(SC520_INTPINPOL,
 316                                 read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
 317
 318         }
 319
 320         /* register the pin */
 321         sc520_pci_ints[pci_pin] = irq;
 322
 323
 324         return 0; /* OK */
 325 }
 326
 327 void pci_sc520_init(struct pci_controller *hose)
 328 {
 329         hose->first_busno = 0;
 330         hose->last_busno = 0xff;
 331
 332         /* System memory space */
 333         pci_set_region(hose->regions + 0,
 334                        SC520_PCI_MEMORY_BUS,
 335                        SC520_PCI_MEMORY_PHYS,
 336                        SC520_PCI_MEMORY_SIZE,
 337                        PCI_REGION_MEM | PCI_REGION_MEMORY);
 338
 339         /* PCI memory space */
 340         pci_set_region(hose->regions + 1,
 341                        SC520_PCI_MEM_BUS,
 342                        SC520_PCI_MEM_PHYS,
 343                        SC520_PCI_MEM_SIZE,
 344                        PCI_REGION_MEM);
 345
 346         /* ISA/PCI memory space */
 347         pci_set_region(hose->regions + 2,
 348                        SC520_ISA_MEM_BUS,
 349                        SC520_ISA_MEM_PHYS,
 350                        SC520_ISA_MEM_SIZE,
 351                        PCI_REGION_MEM);
 352
 353         /* PCI I/O space */
 354         pci_set_region(hose->regions + 3,
 355                        SC520_PCI_IO_BUS,
 356                        SC520_PCI_IO_PHYS,
 357                        SC520_PCI_IO_SIZE,
 358                        PCI_REGION_IO);
 359
 360         /* ISA/PCI I/O space */
 361         pci_set_region(hose->regions + 4,
 362                        SC520_ISA_IO_BUS,
 363                        SC520_ISA_IO_PHYS,
 364                        SC520_ISA_IO_SIZE,
 365                        PCI_REGION_IO);
 366
 367         hose->region_count = 5;
 368
 369         pci_setup_type1(hose,
 370                         SC520_REG_ADDR,
 371                         SC520_REG_DATA);
 372
 373         pci_register_hose(hose);
 374
 375         hose->last_busno = pci_hose_scan(hose);
 376
 377         /* enable target memory acceses on host brige */
 378         pci_write_config_word(0, PCI_COMMAND,
 379                               PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 380
 381 }
 382
 383
 384 #endif
 385
 386 #ifdef CFG_TIMER_SC520
 387
 388
 389 void reset_timer(void)
 390 {
 391         write_mmcr_word(SC520_GPTMR0CNT, 0);
 392         write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
 393
 394 }
 395
 396 ulong get_timer(ulong base)
 397 {
 398         /* fixme: 30 or 33 */
 399         return  read_mmcr_word(SC520_GPTMR0CNT) / 33;
 400 }
 401
 402 void set_timer(ulong t)
 403 {
 404         /* FixMe: use two cascade coupled timers */
 405         write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
 406         write_mmcr_word(SC520_GPTMR0CNT, t*33);
 407         write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
 408 }
 409
 410
 411 void udelay(unsigned long usec)
 412 {
 413         int m=0;
 414         long u;
 415
 416         read_mmcr_word(SC520_SWTMRMILLI);
 417         read_mmcr_word(SC520_SWTMRMICRO);
 418
 419 #if 0
 420         /* do not enable this line, udelay is used in the serial driver -> recursion */
 421         printf("udelay: %ld m.u %d.%d  tm.tu %d.%d\n", usec, m, u, tm, tu);
 422 #endif
 423         while (1) {
 424
 425                 m += read_mmcr_word(SC520_SWTMRMILLI);
 426                 u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
 427
 428                 if (usec <= u) {
 429                         break;
 430                 }
 431         }
 432 }
 433
 434 #endif
 435
 436 int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
 437 {
 438         u8 temp=0;
 439
 440         if (freq >= 8192) {
 441                 temp |= CTL_CLK_SEL_4;
 442         } else if (freq >= 4096) {
 443                 temp |= CTL_CLK_SEL_8;
 444         } else if (freq >= 2048) {
 445                 temp |= CTL_CLK_SEL_16;
 446         } else if (freq >= 1024) {
 447                 temp |= CTL_CLK_SEL_32;
 448         } else if (freq >= 512) {
 449                 temp |= CTL_CLK_SEL_64;
 450         } else if (freq >= 256) {
 451                 temp |= CTL_CLK_SEL_128;
 452         } else if (freq >= 128) {
 453                 temp |= CTL_CLK_SEL_256;
 454         } else {
 455                 temp |= CTL_CLK_SEL_512;
 456         }
 457
 458         if (!lsb_first) {
 459                 temp |= MSBF_ENB;
 460         }
 461
 462         if (inv_clock) {
 463                 temp |= CLK_INV_ENB;
 464         }
 465
 466         if (inv_phase) {
 467                 temp |= PHS_INV_ENB;
 468         }
 469
 470         write_mmcr_byte(SC520_SSICTL, temp);
 471
 472         return 0;
 473 }
 474
 475 u8 ssi_txrx_byte(u8 data)
 476 {
 477         write_mmcr_byte(SC520_SSIXMIT, data);
 478         while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
 479         write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
 480         while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
 481         return read_mmcr_byte(SC520_SSIRCV);
 482 }
 483
 484
 485 void ssi_tx_byte(u8 data)
 486 {
 487         write_mmcr_byte(SC520_SSIXMIT, data);
 488         while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
 489         write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
 490 }
 491
 492 u8 ssi_rx_byte(void)
 493 {
 494         while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
 495         write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
 496         while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
 497         return read_mmcr_byte(SC520_SSIRCV);
 498 }
 499
 500 #endif /* CONFIG_SC520 */