2 * initcode.c - Initialize the processor. This is usually entails things
3 * like external memory, voltage regulators, etc... Note that this file
4 * cannot make any function calls as it may be executed all by itself by
5 * the Blackfin's bootrom in LDR format.
7 * Copyright (c) 2004-2008 Analog Devices Inc.
9 * Licensed under the GPL-2 or later.
13 #include <asm/blackfin.h>
14 #include <asm/mach-common/bits/bootrom.h>
15 #include <asm/mach-common/bits/core.h>
16 #include <asm/mach-common/bits/ebiu.h>
17 #include <asm/mach-common/bits/pll.h>
18 #include <asm/mach-common/bits/uart.h>
20 #define BFIN_IN_INITCODE
23 __attribute__((always_inline))
24 static inline void serial_init(void)
27 # ifdef BFIN_BOOT_UART_USE_RTS
28 # define BFIN_UART_USE_RTS 1
30 # define BFIN_UART_USE_RTS 0
32 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
35 /* force RTS rather than relying on auto RTS */
36 bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL);
38 /* Wait for the line to clear up. We cannot rely on UART
39 * registers as none of them reflect the status of the RSR.
40 * Instead, we'll sleep for ~10 bit times at 9600 baud.
41 * We can precalc things here by assuming boot values for
42 * PLL rather than loading registers and calculating.
43 * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
45 * Divisor = (SCLK / baud) / 16
46 * SCLK = baud * 16 * Divisor
47 * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
48 * CCLK = (16 * Divisor * 5) * (9600 / 10)
49 * In reality, this will probably be just about 1 second delay,
50 * so assuming 9600 baud is OK (both as a very low and too high
51 * speed as this will buffer things enough).
53 #define _NUMBITS (10) /* how many bits to delay */
54 #define _LOWBAUD (9600) /* low baud rate */
55 #define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
56 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
57 #define _NUMINS (3) /* how many instructions in loop */
58 #define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
61 asm volatile("" : : : "memory");
65 if (BFIN_DEBUG_EARLY_SERIAL) {
66 int ucen = *pUART_GCTL & UCEN;
69 /* If the UART is off, that means we need to program
70 * the baud rate ourselves initially.
73 serial_early_set_baud(CONFIG_BAUDRATE);
77 __attribute__((always_inline))
78 static inline void serial_deinit(void)
81 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
82 /* clear forced RTS rather than relying on auto RTS */
83 bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL);
88 __attribute__((always_inline))
89 static inline void serial_putc(char c)
91 if (!BFIN_DEBUG_EARLY_SERIAL)
99 while (!(*pUART_LSR & TEMT))
104 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
105 * us a freq of 16MHz for SPI which should generally be
106 * slow enough for the slow reads the bootrom uses.
108 #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
109 ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
110 (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
111 # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
113 # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
115 #ifndef CONFIG_SPI_BAUD_INITBLOCK
116 # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
119 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
122 /* PLL_DIV defines */
123 #ifndef CONFIG_PLL_DIV_VAL
124 # if (CONFIG_CCLK_DIV == 1)
125 # define CONFIG_CCLK_ACT_DIV CCLK_DIV1
126 # elif (CONFIG_CCLK_DIV == 2)
127 # define CONFIG_CCLK_ACT_DIV CCLK_DIV2
128 # elif (CONFIG_CCLK_DIV == 4)
129 # define CONFIG_CCLK_ACT_DIV CCLK_DIV4
130 # elif (CONFIG_CCLK_DIV == 8)
131 # define CONFIG_CCLK_ACT_DIV CCLK_DIV8
133 # define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
135 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
138 #ifndef CONFIG_PLL_LOCKCNT_VAL
139 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
142 #ifndef CONFIG_PLL_CTL_VAL
143 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
146 #ifndef CONFIG_EBIU_RSTCTL_VAL
147 # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
149 #if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
150 # error invalid EBIU_RSTCTL value: must not set reserved bits
153 #ifndef CONFIG_EBIU_MBSCTL_VAL
154 # define CONFIG_EBIU_MBSCTL_VAL 0
157 #if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
158 # error invalid EBIU_DDRQUE value: must not set reserved bits
161 /* Make sure our voltage value is sane so we don't blow up! */
162 #ifndef CONFIG_VR_CTL_VAL
163 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
164 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
165 # define CCLK_VLEV_120 400000000
166 # define CCLK_VLEV_125 533000000
167 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
168 # define CCLK_VLEV_120 401000000
169 # define CCLK_VLEV_125 401000000
170 # elif defined(__ADSPBF561__)
171 # define CCLK_VLEV_120 300000000
172 # define CCLK_VLEV_125 501000000
174 # if BFIN_CCLK < CCLK_VLEV_120
175 # define CONFIG_VR_CTL_VLEV VLEV_120
176 # elif BFIN_CCLK < CCLK_VLEV_125
177 # define CONFIG_VR_CTL_VLEV VLEV_125
179 # define CONFIG_VR_CTL_VLEV VLEV_130
181 # if defined(__ADSPBF52x__) /* TBD; use default */
182 # undef CONFIG_VR_CTL_VLEV
183 # define CONFIG_VR_CTL_VLEV VLEV_110
184 # elif defined(__ADSPBF54x__) /* TBD; use default */
185 # undef CONFIG_VR_CTL_VLEV
186 # define CONFIG_VR_CTL_VLEV VLEV_120
187 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
188 # undef CONFIG_VR_CTL_VLEV
189 # define CONFIG_VR_CTL_VLEV VLEV_125
192 # ifdef CONFIG_BFIN_MAC
193 # define CONFIG_VR_CTL_CLKBUF CLKBUFOE
195 # define CONFIG_VR_CTL_CLKBUF 0
198 # if defined(__ADSPBF52x__)
199 # define CONFIG_VR_CTL_FREQ FREQ_1000
201 # define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
204 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
207 /* some parts do not have an on-chip voltage regulator */
208 #if defined(__ADSPBF51x__)
209 # define CONFIG_HAS_VR 0
210 # undef CONFIG_VR_CTL_VAL
211 # define CONFIG_VR_CTL_VAL 0
213 # define CONFIG_HAS_VR 1
217 /* Blackfin with SDRAM */
218 #ifndef CONFIG_EBIU_SDBCTL_VAL
219 # if CONFIG_MEM_SIZE == 16
220 # define CONFIG_EBSZ_VAL EBSZ_16
221 # elif CONFIG_MEM_SIZE == 32
222 # define CONFIG_EBSZ_VAL EBSZ_32
223 # elif CONFIG_MEM_SIZE == 64
224 # define CONFIG_EBSZ_VAL EBSZ_64
225 # elif CONFIG_MEM_SIZE == 128
226 # define CONFIG_EBSZ_VAL EBSZ_128
227 # elif CONFIG_MEM_SIZE == 256
228 # define CONFIG_EBSZ_VAL EBSZ_256
229 # elif CONFIG_MEM_SIZE == 512
230 # define CONFIG_EBSZ_VAL EBSZ_512
232 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
234 # if CONFIG_MEM_ADD_WDTH == 8
235 # define CONFIG_EBCAW_VAL EBCAW_8
236 # elif CONFIG_MEM_ADD_WDTH == 9
237 # define CONFIG_EBCAW_VAL EBCAW_9
238 # elif CONFIG_MEM_ADD_WDTH == 10
239 # define CONFIG_EBCAW_VAL EBCAW_10
240 # elif CONFIG_MEM_ADD_WDTH == 11
241 # define CONFIG_EBCAW_VAL EBCAW_11
243 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
245 # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
249 /* Conflicting Column Address Widths Causes SDRAM Errors:
250 * EB2CAW and EB3CAW must be the same
253 # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
254 # error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
258 BOOTROM_CALLED_FUNC_ATTR
259 void initcode(ADI_BOOT_DATA *bootstruct)
261 ADI_BOOT_DATA bootstruct_scratch;
263 /* Save the clock pieces that are used in baud rate calculation */
264 unsigned int sdivB, divB, vcoB;
266 if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
267 sdivB = bfin_read_PLL_DIV() & 0xf;
268 vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
269 divB = serial_early_get_div();
274 /* If the bootstruct is NULL, then it's because we're loading
275 * dynamically and not via LDR (bootrom). So set the struct to
276 * some scratch space.
279 bootstruct = &bootstruct_scratch;
281 #ifdef CONFIG_HW_WATCHDOG
282 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
283 # define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
285 /* Program the watchdog with an initial timeout of ~20 seconds.
286 * Hopefully that should be long enough to load the u-boot LDR
287 * (from wherever) and then the common u-boot code can take over.
288 * In bypass mode, the start.S would have already set a much lower
289 * timeout, so don't clobber that.
291 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
292 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
293 bfin_write_WDOG_CTL(0);
299 /* If external memory is enabled, put it into self refresh first. */
300 bool put_into_srfs = false;
302 if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
303 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
304 put_into_srfs = true;
307 if (bfin_read_EBIU_SDBCTL() & EBE) {
308 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
309 put_into_srfs = true;
315 /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
316 * fast read, so we need to slow down the SPI clock a lot more during
317 * boot. Once we switch over to u-boot's SPI flash driver, we'll
318 * increase the speed appropriately.
320 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
321 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
322 bootstruct->dFlags |= BFLAG_FASTREAD;
323 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
328 /* If we're entering self refresh, make sure it has happened. */
331 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
333 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
339 /* With newer bootroms, we use the helper function to set up
340 * the memory controller. Older bootroms lacks such helpers
341 * so we do it ourselves.
343 uint16_t vr_ctl = bfin_read_VR_CTL();
344 if (!ANOMALY_05000386) {
347 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
348 ADI_SYSCTRL_VALUES memory_settings;
349 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT;
351 actions |= SYSCTRL_VRCTL;
352 if (CONFIG_VR_CTL_VAL & FREQ_MASK)
353 actions |= SYSCTRL_INTVOLTAGE;
355 actions |= SYSCTRL_EXTVOLTAGE;
356 memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
358 actions |= SYSCTRL_EXTVOLTAGE;
359 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
360 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
361 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
363 bfin_write_SIC_IWR1(0);
365 bfrom_SysControl(actions, &memory_settings, NULL);
367 bfin_write_SIC_IWR1(-1);
370 bfin_write_SICA_IWR0(-1);
371 bfin_write_SICA_IWR1(-1);
376 /* Disable all peripheral wakeups except for the PLL event. */
378 bfin_write_SIC_IWR0(1);
379 bfin_write_SIC_IWR1(0);
381 bfin_write_SIC_IWR2(0);
383 #elif defined(SICA_IWR0)
384 bfin_write_SICA_IWR0(1);
385 bfin_write_SICA_IWR1(0);
387 bfin_write_SIC_IWR(1);
392 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
393 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
397 /* Only reprogram when needed to avoid triggering unnecessary
398 * PLL relock sequences.
400 if (vr_ctl != CONFIG_VR_CTL_VAL) {
402 bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
408 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
412 /* Only reprogram when needed to avoid triggering unnecessary
413 * PLL relock sequences.
415 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
417 bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
423 /* Restore all peripheral wakeups. */
425 bfin_write_SIC_IWR0(-1);
426 bfin_write_SIC_IWR1(-1);
428 bfin_write_SIC_IWR2(-1);
430 #elif defined(SICA_IWR0)
431 bfin_write_SICA_IWR0(-1);
432 bfin_write_SICA_IWR1(-1);
434 bfin_write_SIC_IWR(-1);
440 /* Since we've changed the SCLK above, we may need to update
441 * the UART divisors (UART baud rates are based on SCLK).
442 * Do the division by hand as there are no native instructions
443 * for dividing which means we'd generate a libgcc reference.
445 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
446 unsigned int sdivR, vcoR;
447 sdivR = bfin_read_PLL_DIV() & 0xf;
448 vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
449 int dividend = sdivB * divB * vcoR;
450 int divisor = vcoB * sdivR;
451 unsigned int quotient;
452 for (quotient = 0; dividend > 0; ++quotient)
454 serial_early_put_div(quotient - ANOMALY_05000230);
459 /* Program the external memory controller before we come out of
460 * self-refresh. This only works with our SDRAM controller.
463 bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
464 bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
465 bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
470 /* Now that we've reprogrammed, take things out of self refresh. */
473 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
475 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
480 /* Our DDR controller sucks and cannot be programmed while in
481 * self-refresh. So we have to pull it out before programming.
484 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
485 bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
486 bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
487 bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
488 # ifdef CONFIG_EBIU_DDRCTL3_VAL
489 /* default is disable, so don't need to force this */
490 bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
492 # ifdef CONFIG_EBIU_DDRQUE_VAL
493 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
499 /* Are we coming out of hibernate (suspend to memory) ?
500 * The memory layout is:
501 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
502 * 0x4: return address
505 * SCKELOW is unreliable on older parts (anomaly 307)
507 if (ANOMALY_05000307 || vr_ctl & 0x8000) {
508 uint32_t *hibernate_magic = 0;
509 __builtin_bfin_ssync(); /* make sure memory controller is done */
510 if (hibernate_magic[0] == 0xDEADBEEF) {
512 bfin_write_EVT15(hibernate_magic[1]);
513 bfin_write_IMASK(EVT_IVG15);
514 __asm__ __volatile__ (
515 /* load reti early to avoid anomaly 281 */
517 /* clear hibernate magic */
519 /* load stack pointer */
521 /* lower ourselves from reset ivg to ivg15 */
525 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
532 /* Program the async banks controller. */
533 bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
534 bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
535 bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
538 /* Not all parts have these additional MMRs. */
539 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
540 bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
541 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
546 /* tell the bootrom where our entry point is */
547 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
548 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);