cpu/bf561/cache.S

   1 #define ASSEMBLY
   2 #include <asm/linkage.h>
   3 #include <config.h>
   4 #include <asm/blackfin.h>
   5 #include <asm/mach-common/bits/mpu.h>
   6
   7 .text
   8 .align 2
   9 ENTRY(_blackfin_icache_flush_range)
  10         R2 = -32;
  11         R2 = R0 & R2;
  12         P0 = R2;
  13         P1 = R1;
  14         CSYNC;
  15         1:
  16         IFLUSH[P0++];
  17         CC = P0 < P1(iu);
  18         IF CC JUMP 1b(bp);
  19         IFLUSH[P0];
  20         SSYNC;
  21         RTS;
  22
  23 ENTRY(_blackfin_dcache_flush_range)
  24         R2 = -32;
  25         R2 = R0 & R2;
  26         P0 = R2;
  27         P1 = R1;
  28         CSYNC;
  29 1:
  30         FLUSH[P0++];
  31         CC = P0 < P1(iu);
  32         IF CC JUMP 1b(bp);
  33         FLUSH[P0];
  34         SSYNC;
  35         RTS;
  36
  37 ENTRY(_icache_invalidate)
  38 ENTRY(_invalidate_entire_icache)
  39         [--SP] = (R7:5);
  40
  41         P0.L = (IMEM_CONTROL & 0xFFFF);
  42         P0.H = (IMEM_CONTROL >> 16);
  43         R7 =[P0];
  44
  45         /*
  46          * Clear the IMC bit , All valid bits in the instruction
  47          * cache are set to the invalid state
  48          */
  49         BITCLR(R7, IMC_P);
  50         CLI R6;
  51         /* SSYNC required before invalidating cache. */
  52         SSYNC;
  53         .align 8;
  54         [P0] = R7;
  55         SSYNC;
  56         STI R6;
  57
  58         /* Configures the instruction cache agian */
  59         R6 = (IMC | ENICPLB);
  60         R7 = R7 | R6;
  61
  62         CLI R6;
  63         SSYNC;
  64         .align 8;
  65         [P0] = R7;
  66         SSYNC;
  67         STI R6;
  68
  69         (R7:5) =[SP++];
  70         RTS;
  71
  72 /*
  73  * Invalidate the Entire Data cache by
  74  * clearing DMC[1:0] bits
  75  */
  76 ENTRY(_invalidate_entire_dcache)
  77 ENTRY(_dcache_invalidate)
  78         [--SP] = (R7:6);
  79
  80         P0.L = (DMEM_CONTROL & 0xFFFF);
  81         P0.H = (DMEM_CONTROL >> 16);
  82         R7 =[P0];
  83
  84         /*
  85          * Clear the DMC[1:0] bits, All valid bits in the data
  86          * cache are set to the invalid state
  87          */
  88         BITCLR(R7, DMC0_P);
  89         BITCLR(R7, DMC1_P);
  90         CLI R6;
  91         SSYNC;
  92         .align 8;
  93         [P0] = R7;
  94         SSYNC;
  95         STI R6;
  96         /* Configures the data cache again */
  97
  98         R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
  99         R7 = R7 | R6;
 100
 101         CLI R6;
 102         SSYNC;
 103         .align 8;
 104         [P0] = R7;
 105         SSYNC;
 106         STI R6;
 107
 108         (R7:6) =[SP++];
 109         RTS;
 110
 111 ENTRY(_blackfin_dcache_invalidate_range)
 112         R2 = -32;
 113         R2 = R0 & R2;
 114         P0 = R2;
 115         P1 = R1;
 116         CSYNC;
 117 1:
 118         FLUSHINV[P0++];
 119         CC = P0 < P1(iu);
 120         IF CC JUMP 1b(bp);
 121
 122         /*
 123          * If the data crosses a cache line, then we'll be pointing to
 124          * the last cache line, but won't have flushed/invalidated it yet, so do
 125          * one more.
 126          */
 127         FLUSHINV[P0];
 128         SSYNC;
 129         RTS;