3 #include <linux/config.h>
5 #include <asm/blackfin.h>
6 #include <asm/mem_init.h>
9 #if (BFIN_BOOT_MODE != BF537_UART_BOOT)
10 #if (CONFIG_CCLK_DIV == 1)
11 #define CONFIG_CCLK_ACT_DIV CCLK_DIV1
13 #if (CONFIG_CCLK_DIV == 2)
14 #define CONFIG_CCLK_ACT_DIV CCLK_DIV2
16 #if (CONFIG_CCLK_DIV == 4)
17 #define CONFIG_CCLK_ACT_DIV CCLK_DIV4
19 #if (CONFIG_CCLK_DIV == 8)
20 #define CONFIG_CCLK_ACT_DIV CCLK_DIV8
22 #ifndef CONFIG_CCLK_ACT_DIV
23 #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
33 #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
42 r0.l = CONFIG_SPI_BAUD_INITBLOCK;
47 #if (BFIN_BOOT_MODE != BF537_UART_BOOT)
50 /* Enable PHY CLK buffer output */
59 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
61 p0.h = hi(PLL_LOCKCNT);
62 p0.l = lo(PLL_LOCKCNT);
68 * Put SDRAM in self-refresh, incase anything is running
70 P2.H = hi(EBIU_SDGCTL);
71 P2.L = lo(EBIU_SDGCTL);
78 * Set PLL_CTL with the value that we calculate in R0
79 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
80 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
81 * - [7] = output delay (add 200ps of delay to mem signals)
82 * - [6] = input delay (add 200ps of input delay to mem signals)
83 * - [5] = PDWN : 1=All Clocks off
84 * - [3] = STOPCK : 1=Core Clock off
85 * - [1] = PLL_OFF : 1=Disable Power to PLL
86 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
87 * all other bits set to zero
90 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
91 r0 = r0 << 9; /* Shift it over */
92 r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
94 r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
95 r1 = r1 << 8; /* Shift it over */
96 r0 = r1 | r0; /* add them all together */
99 p0.l = lo(PLL_CTL); /* Load the address */
100 cli r2; /* Disable interrupts */
102 w[p0] = r0.l; /* Set the value */
103 idle; /* Wait for the PLL to stablize */
104 sti r2; /* Enable interrupts */
111 if ! CC jump check_again;
113 /* Configure SCLK & CCLK Dividers */
114 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
122 * We now are running at speed, time to set the Async mem bank wait states
123 * This will speed up execution, since we are normally running from FLASH.
126 p2.h = (EBIU_AMBCTL1 >> 16);
127 p2.l = (EBIU_AMBCTL1 & 0xFFFF);
128 r0.h = (AMBCTL1VAL >> 16);
129 r0.l = (AMBCTL1VAL & 0xFFFF);
133 p2.h = (EBIU_AMBCTL0 >> 16);
134 p2.l = (EBIU_AMBCTL0 & 0xFFFF);
135 r0.h = (AMBCTL0VAL >> 16);
136 r0.l = (AMBCTL0VAL & 0xFFFF);
140 p2.h = (EBIU_AMGCTL >> 16);
141 p2.l = (EBIU_AMGCTL & 0xffff);
147 * Now, Initialize the SDRAM,
148 * start with the SDRAM Refresh Rate Control Register
150 p0.l = lo(EBIU_SDRRC);
151 p0.h = hi(EBIU_SDRRC);
157 * SDRAM Memory Bank Control Register - bank specific parameters
159 p0.l = (EBIU_SDBCTL & 0xFFFF);
160 p0.h = (EBIU_SDBCTL >> 16);
166 * SDRAM Global Control Register - global programmable parameters
167 * Disable self-refresh
169 P2.H = hi(EBIU_SDGCTL);
170 P2.L = lo(EBIU_SDGCTL);
175 * Check if SDRAM is already powered up, if it is, enable self-refresh
177 p0.h = hi(EBIU_SDSTAT);
178 p0.l = lo(EBIU_SDSTAT);
188 /* Write in the new value in the register */
189 R0.L = lo(mem_SDGCTL);
190 R0.H = hi(mem_SDGCTL);