cpu/at32ap/pm.c

   1 /*
   2  * Copyright (C) 2006 Atmel Corporation
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 #include <common.h>
  23
  24 #ifdef CFG_POWER_MANAGER
  25 #include <asm/errno.h>
  26 #include <asm/io.h>
  27
  28 #include <asm/arch/memory-map.h>
  29 #include <asm/arch/platform.h>
  30
  31 #include "sm.h"
  32
  33 /* Sanity checks */
  34 #if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB)           \
  35         || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA)    \
  36         || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
  37 # error Constraint fCPU >= fHSB >= fPB{A,B} violated
  38 #endif
  39 #if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
  40 # error Invalid PLL multiplier and/or divider
  41 #endif
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 struct clock_domain_state {
  46         const struct device *bridge;
  47         unsigned long freq;
  48         u32 mask;
  49 };
  50 static struct clock_domain_state ckd_state[NR_CLOCK_DOMAINS];
  51
  52 int pm_enable_clock(enum clock_domain_id id, unsigned int index)
  53 {
  54         const struct clock_domain *ckd = &chip_clock[id];
  55         struct clock_domain_state *state = &ckd_state[id];
  56
  57         if (ckd->bridge != NO_DEVICE) {
  58                 state->bridge = get_device(ckd->bridge);
  59                 if (!state->bridge)
  60                         return -EBUSY;
  61         }
  62
  63         state->mask |= 1 << index;
  64         if (gd->sm)
  65                 writel(state->mask, gd->sm->regs + ckd->reg);
  66
  67         return 0;
  68 }
  69
  70 void pm_disable_clock(enum clock_domain_id id, unsigned int index)
  71 {
  72         const struct clock_domain *ckd = &chip_clock[id];
  73         struct clock_domain_state *state = &ckd_state[id];
  74
  75         state->mask &= ~(1 << index);
  76         if (gd->sm)
  77                 writel(state->mask, gd->sm->regs + ckd->reg);
  78
  79         if (ckd->bridge)
  80                 put_device(state->bridge);
  81 }
  82
  83 unsigned long pm_get_clock_freq(enum clock_domain_id domain)
  84 {
  85         return ckd_state[domain].freq;
  86 }
  87
  88 void pm_init(void)
  89 {
  90         uint32_t cksel = 0;
  91         unsigned long main_clock;
  92
  93         /* Make sure we don't disable any device we're already using */
  94         get_device(DEVICE_HRAMC);
  95         get_device(DEVICE_HEBI);
  96
  97         /* Enable the PICO as well */
  98         ckd_state[CLOCK_CPU].mask |= 1;
  99
 100         gd->sm = get_device(DEVICE_SM);
 101         if (!gd->sm)
 102                 panic("Unable to claim system manager device!\n");
 103
 104         /* Disable any devices that haven't been explicitly claimed */
 105         sm_writel(gd->sm, PM_PBB_MASK, ckd_state[CLOCK_PBB].mask);
 106         sm_writel(gd->sm, PM_PBA_MASK, ckd_state[CLOCK_PBA].mask);
 107         sm_writel(gd->sm, PM_HSB_MASK, ckd_state[CLOCK_HSB].mask);
 108         sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask);
 109
 110 #ifdef CONFIG_PLL
 111         /* Initialize the PLL */
 112         main_clock = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL;
 113
 114         sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
 115                                     | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
 116                                     | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
 117                                     | SM_BF(PLLOPT, CFG_PLL0_OPT)
 118                                     | SM_BF(PLLOSC, 0)
 119                                     | SM_BIT(PLLEN)));
 120
 121         /* Wait for lock */
 122         while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ;
 123 #else
 124         main_clock = CFG_OSC0_HZ;
 125 #endif
 126
 127         /* Set up clocks for the CPU and all peripheral buses */
 128         if (CFG_CLKDIV_CPU) {
 129                 cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
 130                 ckd_state[CLOCK_CPU].freq = main_clock / (1 << CFG_CLKDIV_CPU);
 131         } else {
 132                 ckd_state[CLOCK_CPU].freq = main_clock;
 133         }
 134         if (CFG_CLKDIV_HSB) {
 135                 cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
 136                 ckd_state[CLOCK_HSB].freq = main_clock / (1 << CFG_CLKDIV_HSB);
 137         } else {
 138                 ckd_state[CLOCK_HSB].freq = main_clock;
 139         }
 140         if (CFG_CLKDIV_PBA) {
 141                 cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
 142                 ckd_state[CLOCK_PBA].freq = main_clock / (1 << CFG_CLKDIV_PBA);
 143         } else {
 144                 ckd_state[CLOCK_PBA].freq = main_clock;
 145         }
 146         if (CFG_CLKDIV_PBB) {
 147                 cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
 148                 ckd_state[CLOCK_PBB].freq = main_clock / (1 << CFG_CLKDIV_PBB);
 149         } else {
 150                 ckd_state[CLOCK_PBB].freq = main_clock;
 151         }
 152         sm_writel(gd->sm, PM_CKSEL, cksel);
 153
 154         /* CFG_HZ currently depends on cpu_hz */
 155         gd->cpu_hz = ckd_state[CLOCK_CPU].freq;
 156
 157 #ifdef CONFIG_PLL
 158         /* Use PLL0 as main clock */
 159         sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL));
 160 #endif
 161 }
 162
 163 #endif /* CFG_POWER_MANAGER */