2 * Copyright (C) 2005-2006 Atmel Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifdef CONFIG_SYS_HSDRAMC
26 #include <asm/sdram.h>
28 #include <asm/arch/clk.h>
29 #include <asm/arch/memory-map.h>
33 unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
35 unsigned long sdram_size;
39 cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
40 | HSDRAMC1_BF(NR, config->row_bits - 11)
41 | HSDRAMC1_BF(NB, config->bank_bits - 1)
42 | HSDRAMC1_BF(CAS, config->cas)
43 | HSDRAMC1_BF(TWR, config->twr)
44 | HSDRAMC1_BF(TRC, config->trc)
45 | HSDRAMC1_BF(TRP, config->trp)
46 | HSDRAMC1_BF(TRCD, config->trcd)
47 | HSDRAMC1_BF(TRAS, config->tras)
48 | HSDRAMC1_BF(TXSR, config->txsr));
50 if (config->data_bits == SDRAM_DATA_16BIT)
51 cfgreg |= HSDRAMC1_BIT(DBW);
53 hsdramc1_writel(CR, cfgreg);
55 /* Send a NOP to turn on the clock (necessary on some chips) */
56 hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
58 writel(0, sdram_base);
61 * Initialization sequence for SDRAM, from the data sheet:
63 * 1. A minimum pause of 200 us is provided to precede any
69 * 2. A Precharge All command is issued to the SDRAM
71 hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
73 writel(0, sdram_base);
76 * 3. Eight auto-refresh (CBR) cycles are provided
78 hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
80 for (i = 0; i < 8; i++)
81 writel(0, sdram_base);
84 * 4. A mode register set (MRS) cycle is issued to program
85 * SDRAM parameters, in particular CAS latency and burst
88 * The address will be chosen by the SDRAMC automatically; we
89 * just have to make sure BA[1:0] are set to 0.
91 hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
93 writel(0, sdram_base);
96 * 5. The application must go into Normal Mode, setting Mode
97 * to 0 in the Mode Register and performing a write access
98 * at any location in the SDRAM.
100 hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
102 writel(0, sdram_base);
105 * 6. Write refresh rate into SDRAMC refresh timer count
106 * register (refresh rate = timing between refresh cycles).
108 hsdramc1_writel(TR, config->refresh_period);
110 if (config->data_bits == SDRAM_DATA_16BIT)
111 sdram_size = 1 << (config->row_bits + config->col_bits
112 + config->bank_bits + 1);
114 sdram_size = 1 << (config->row_bits + config->col_bits
115 + config->bank_bits + 2);
120 #endif /* CONFIG_SYS_HSDRAMC */