cpu/arm_cortexa8/s5pc1xx/usb-hs-otg.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22
  23 #include <command.h>
  24 #include <asm/errno.h>
  25 #include <asm/arch/power.h>
  26 #include "usb-hs-otg.h"
  27
  28 #define SUSPEND_RESUME_ON 0
  29
  30 u32 remode_wakeup;
  31 u16 config_value;
  32
  33 int s5p_receive_done;
  34 int s5p_got_header;
  35 int s5p_usb_connected;
  36
  37 USB_OPMODE op_mode = USB_CPU;
  38 USB_SPEED speed = USB_HIGH;
  39 /*
  40 USB_OPMODE op_mode = USB_DMA;
  41 USB_SPEED speed = USB_FULL;
  42 */
  43
  44 otg_dev_t otg;
  45 get_status_t get_status;
  46 get_intf_t get_intf;
  47
  48 enum EP_INDEX {
  49         EP0, EP1, EP2, EP3, EP4
  50 };
  51
  52 /*------------------------------------------------*/
  53 /* EP0 state */
  54 enum EP0_STATE {
  55         EP0_STATE_INIT = 0,
  56         EP0_STATE_GD_DEV_0 = 11,
  57         EP0_STATE_GD_DEV_1 = 12,
  58         EP0_STATE_GD_DEV_2 = 13,
  59         EP0_STATE_GD_CFG_0 = 21,
  60         EP0_STATE_GD_CFG_1 = 22,
  61         EP0_STATE_GD_CFG_2 = 23,
  62         EP0_STATE_GD_CFG_3 = 24,
  63         EP0_STATE_GD_CFG_4 = 25,
  64         EP0_STATE_GD_STR_I0 = 30,
  65         EP0_STATE_GD_STR_I1 = 31,
  66         EP0_STATE_GD_STR_I2 = 32,
  67         EP0_STATE_GD_DEV_QUALIFIER = 33,
  68         EP0_STATE_INTERFACE_GET = 34,
  69         EP0_STATE_GET_STATUS0 = 35,
  70         EP0_STATE_GET_STATUS1 = 36,
  71         EP0_STATE_GET_STATUS2 = 37,
  72         EP0_STATE_GET_STATUS3 = 38,
  73         EP0_STATE_GET_STATUS4 = 39,
  74         EP0_STATE_GD_OTHER_SPEED = 40,
  75         EP0_STATE_GD_CFG_ONLY_0 = 41,
  76         EP0_STATE_GD_CFG_ONLY_1 = 42,
  77         EP0_STATE_GD_IF_ONLY_0 = 44,
  78         EP0_STATE_GD_IF_ONLY_1 = 45,
  79         EP0_STATE_GD_EP0_ONLY_0 = 46,
  80         EP0_STATE_GD_EP1_ONLY_0 = 47,
  81         EP0_STATE_GD_EP2_ONLY_0 = 48,
  82         EP0_STATE_GD_EP3_ONLY_0 = 49,
  83         EP0_STATE_GD_OTHER_SPEED_HIGH_1 = 51,
  84         EP0_STATE_GD_OTHER_SPEED_HIGH_2 = 52,
  85         EP0_STATE_GD_OTHER_SPEED_HIGH_3 = 53
  86 };
  87
  88 /*definitions related to CSR setting */
  89
  90 /* OTG_GOTGCTL*/
  91 #define B_SESSION_VALID         (0x1 << 19)
  92 #define A_SESSION_VALID         (0x1 << 18)
  93
  94 /* OTG_GAHBCFG*/
  95 #define PTXFE_HALF              (0<<8)
  96 #define PTXFE_ZERO              (1<<8)
  97 #define NPTXFE_HALF             (0<<7)
  98 #define NPTXFE_ZERO             (1<<7)
  99 #define MODE_SLAVE              (0<<5)
 100 #define MODE_DMA                (1<<5)
 101 #define BURST_SINGLE            (0<<1)
 102 #define BURST_INCR              (1<<1)
 103 #define BURST_INCR4             (3<<1)
 104 #define BURST_INCR8             (5<<1)
 105 #define BURST_INCR16            (7<<1)
 106 #define GBL_INT_UNMASK          (1<<0)
 107 #define GBL_INT_MASK            (0<<0)
 108
 109 /* OTG_GRSTCTL*/
 110 #define AHB_MASTER_IDLE         (1u<<31)
 111 #define CORE_SOFT_RESET         (0x1<<0)
 112
 113 /* OTG_GINTSTS/OTG_GINTMSK core interrupt register */
 114 #define INT_RESUME              (1u<<31)
 115 #define INT_DISCONN             (0x1<<29)
 116 #define INT_CONN_ID_STS_CNG     (0x1<<28)
 117 #define INT_OUT_EP              (0x1<<19)
 118 #define INT_IN_EP               (0x1<<18)
 119 #define INT_ENUMDONE            (0x1<<13)
 120 #define INT_RESET               (0x1<<12)
 121 #define INT_SUSPEND             (0x1<<11)
 122 #define INT_TX_FIFO_EMPTY       (0x1<<5)
 123 #define INT_RX_FIFO_NOT_EMPTY   (0x1<<4)
 124 #define INT_SOF                 (0x1<<3)
 125 #define INT_DEV_MODE            (0x0<<0)
 126 #define INT_HOST_MODE           (0x1<<1)
 127 #define INT_OTG                 (0x1<<2)
 128
 129 /* OTG_GRXSTSP STATUS*/
 130 #define GLOBAL_OUT_NAK                  (0x1<<17)
 131 #define OUT_PKT_RECEIVED                (0x2<<17)
 132 #define OUT_TRNASFER_COMPLETED          (0x3<<17)
 133 #define SETUP_TRANSACTION_COMPLETED     (0x4<<17)
 134 #define SETUP_PKT_RECEIVED              (0x6<<17)
 135
 136 /* OTG_DCTL device control register */
 137 #define NORMAL_OPERATION                (0x1<<0)
 138 #define SOFT_DISCONNECT                 (0x1<<1)
 139 #define TEST_J_MODE                     (TEST_J<<4)
 140 #define TEST_K_MODE                     (TEST_K<<4)
 141 #define TEST_SE0_NAK_MODE               (TEST_SE0_NAK<<4)
 142 #define TEST_PACKET_MODE                (TEST_PACKET<<4)
 143 #define TEST_FORCE_ENABLE_MODE          (TEST_FORCE_ENABLE<<4)
 144 #define TEST_CONTROL_FIELD              (0x7<<4)
 145
 146 /* OTG_DAINT device all endpoint interrupt register */
 147 #define INT_IN_EP0                      (0x1<<0)
 148 #define INT_IN_EP1                      (0x1<<1)
 149 #define INT_IN_EP3                      (0x1<<3)
 150 #define INT_OUT_EP0                     (0x1<<16)
 151 #define INT_OUT_EP2                     (0x1<<18)
 152 #define INT_OUT_EP4                     (0x1<<20)
 153
 154 /* OTG_DIEPCTL0/OTG_DOEPCTL0 */
 155 #define DEPCTL_EPENA                    (0x1<<31)
 156 #define DEPCTL_EPDIS                    (0x1<<30)
 157 #define DEPCTL_SNAK                     (0x1<<27)
 158 #define DEPCTL_CNAK                     (0x1<<26)
 159 #define DEPCTL_CTRL_TYPE                (EP_TYPE_CONTROL<<18)
 160 #define DEPCTL_ISO_TYPE                 (EP_TYPE_ISOCHRONOUS<<18)
 161 #define DEPCTL_BULK_TYPE                (EP_TYPE_BULK<<18)
 162 #define DEPCTL_INTR_TYPE                (EP_TYPE_INTERRUPT<<18)
 163 #define DEPCTL_USBACTEP                 (0x1<<15)
 164
 165 /*ep0 enable, clear nak, next ep0, max 64byte */
 166 #define EPEN_CNAK_EP0_64 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(0<<0))
 167
 168 /*ep0 enable, clear nak, next ep0, 8byte */
 169 #define EPEN_CNAK_EP0_8 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(3<<0))
 170
 171 /* DIEPCTLn/DOEPCTLn */
 172 #define BACK2BACK_SETUP_RECEIVED        (0x1<<6)
 173 #define INTKN_TXFEMP                    (0x1<<4)
 174 #define NON_ISO_IN_EP_TIMEOUT           (0x1<<3)
 175 #define CTRL_OUT_EP_SETUP_PHASE_DONE    (0x1<<3)
 176 #define AHB_ERROR                       (0x1<<2)
 177 #define TRANSFER_DONE                   (0x1<<0)
 178
 179 /* codes representing languages */
 180 const u8 string_desc0[] = {
 181         4, STRING_DESCRIPTOR, LANGID_US_L, LANGID_US_H,
 182 };
 183
 184 #ifdef CONFIG_SAMSUNG_USB
 185 const u8 string_desc1[] =       /* Manufacturer */
 186 {
 187         (0x14 + 2), STRING_DESCRIPTOR,
 188         'S', 0x0, '/', 0x0, 'W', 0x0, ' ', 0x0, 'C', 0x0,
 189         'e', 0x0, 'n', 0x0, 't', 0x0, 'e', 0x0, 'r', 0x0,
 190 };
 191 #else
 192 const u8 string_desc1[] =       /* Manufacturer */
 193 {
 194         (0x14 + 2), STRING_DESCRIPTOR,
 195         'S', 0x0, 'y', 0x0, 's', 0x0, 't', 0x0, 'e', 0x0,
 196         'm', 0x0, ' ', 0x0, 'M', 0x0, 'C', 0x0, 'U', 0x0,
 197 };
 198 #endif
 199
 200 #ifdef CONFIG_SAMSUNG_USB
 201 const u8 string_desc2[] =       /* Product */
 202 {
 203         (0x22 + 2), STRING_DESCRIPTOR,
 204         'S', 0x0, 'A', 0x0, 'M', 0x0, 'S', 0x0, 'U', 0x0,
 205         'N', 0x0, 'G', 0x0, ' ', 0x0, 'X', 0x0, 'O', 0x0,
 206         ' ', 0x0, 'D', 0x0, 'R', 0x0, 'I', 0x0, 'V', 0x0,
 207         'E', 0x0, 'R', 0x0
 208 };
 209 #else
 210 const u8 string_desc2[] =       /* Product */
 211 {
 212         (0x2a + 2), STRING_DESCRIPTOR,
 213         'S', 0x0, 'E', 0x0, 'C', 0x0, ' ', 0x0, 'S', 0x0,
 214         '3', 0x0, 'C', 0x0, '6', 0x0, '4', 0x0, '0', 0x0,
 215         '0', 0x0, 'X', 0x0, ' ', 0x0, 'T', 0x0, 'e', 0x0,
 216         's', 0x0, 't', 0x0, ' ', 0x0, 'B', 0x0, '/', 0x0,
 217         'D', 0x0
 218 };
 219 #endif
 220
 221 /* setting the device qualifier descriptor and a string descriptor */
 222 const u8 qualifier_desc[] = {
 223         0x0a,           /*  0 desc size */
 224         0x06,           /*  1 desc type (DEVICE_QUALIFIER) */
 225         0x00,           /*  2 USB release */
 226         0x02,           /*  3 => 2.00 */
 227         0xFF,           /*  4 class */
 228         0x00,           /*  5 subclass */
 229         0x00,           /*  6 protocol */
 230         64,             /*  7 max pack size */
 231         0x01,           /*  8 number of other-speed configuration */
 232         0x00,           /*  9 reserved */
 233 };
 234
 235 const u8 config_full[] = {
 236         0x09,           /*  0 desc size */
 237         0x07,           /*  1 desc type (other speed) */
 238         0x20,           /*  2 Total length of data returned */
 239         0x00,           /*  3 */
 240         0x01,           /*  4 Number of interfaces */
 241         0x01,           /*  5 value to use to select configuration */
 242         0x00,           /*  6 index of string desc */
 243         /*  7 same as configuration desc */
 244         CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED,
 245         0x19,           /*  8 same as configuration desc */
 246
 247 };
 248
 249 const u8 config_full_total[] = {
 250         0x09, 0x07, 0x20, 0x00, 0x01, 0x01, 0x00, 0xC0, 0x19,
 251         0x09, 0x04, 0x00, 0x00, 0x02, 0xff, 0x00, 0x00, 0x00,
 252         0x07, 0x05, 0x83, 0x02, 0x40, 0x00, 0x00,
 253         0x07, 0x05, 0x04, 0x02, 0x40, 0x00, 0x00
 254 };
 255
 256 const u8 config_high[] = {
 257         0x09,           /*  0 desc size */
 258         0x07,           /*  1 desc type (other speed) */
 259         0x20,           /*  2 Total length of data returned */
 260         0x00,           /*  3 */
 261         0x01,           /*  4 Number of interfaces */
 262         0x01,           /*  5 value to use to select configuration */
 263         0x00,           /*  6 index of string desc */
 264         /*  7 same as configuration desc */
 265         CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED,
 266         0x19,                   /*  8 same as configuration desc */
 267
 268 };
 269
 270 const u8 config_high_total[] = {
 271         0x09, 0x07, 0x20, 0x00, 0x01, 0x01, 0x00, 0xC0, 0x19,
 272         0x09, 0x04, 0x00, 0x00, 0x02, 0xff, 0x00, 0x00, 0x00,
 273         0x07, 0x05, 0x81, 0x02, 0x00, 0x02, 0x00,
 274         0x07, 0x05, 0x02, 0x02, 0x00, 0x02, 0x00
 275 };
 276
 277 /* Descriptor size */
 278 enum DESCRIPTOR_SIZE {
 279         DEVICE_DESC_SIZE = sizeof(device_desc_t),
 280         STRING_DESC0_SIZE = sizeof(string_desc0),
 281         STRING_DESC1_SIZE = sizeof(string_desc1),
 282         STRING_DESC2_SIZE = sizeof(string_desc2),
 283         CONFIG_DESC_SIZE = sizeof(config_desc_t),
 284         INTERFACE_DESC_SIZE = sizeof(intf_desc_t),
 285         ENDPOINT_DESC_SIZE = sizeof(ep_desc_t),
 286         DEVICE_QUALIFIER_SIZE = sizeof(qualifier_desc),
 287         OTHER_SPEED_CFG_SIZE = 9
 288 };
 289
 290 /*32 <cfg desc>+<if desc>+<endp0 desc>+<endp1 desc>*/
 291 #define CONFIG_DESC_TOTAL_SIZE  \
 292         (CONFIG_DESC_SIZE+INTERFACE_DESC_SIZE+ENDPOINT_DESC_SIZE*2)
 293
 294 static unsigned int phy_base;
 295 static unsigned int otg_base;
 296
 297 static inline void s5p_usb_init_base(void)
 298 {
 299         if (cpu_is_s5pc110()) {
 300                 phy_base = S5PC110_PHY_BASE;
 301                 otg_base = S5PC110_OTG_BASE;
 302         } else {
 303                 phy_base = S5PC100_PHY_BASE;
 304                 otg_base = S5PC100_OTG_BASE;
 305         }
 306 }
 307
 308 static inline int s5pc1xx_phy_read_reg(int offset)
 309 {
 310         return readl(phy_base + offset);
 311 }
 312
 313 static inline void s5pc1xx_phy_write_reg(int value, int offset)
 314 {
 315         writel(value, phy_base + offset);
 316 }
 317
 318 static inline int s5pc1xx_otg_read_reg(int offset)
 319 {
 320         return readl(otg_base + offset);
 321 }
 322
 323 static inline void s5pc1xx_otg_write_reg(int value, int offset)
 324 {
 325         writel(value, otg_base + offset);
 326 }
 327
 328 void s5p_usb_init_phy(void)
 329 {
 330         if (cpu_is_s5pc110()) {
 331                 s5pc1xx_phy_write_reg(0xA0, OTG_PHYPWR);
 332                 s5pc1xx_phy_write_reg(0x3, OTG_PHYCTRL);
 333         } else {
 334                 s5pc1xx_phy_write_reg(0x0, OTG_PHYPWR);
 335 #ifdef CONFIG_OTG_CLK_OSCC
 336                 s5pc1xx_phy_write_reg(0x22, OTG_PHYCTRL);
 337 #else
 338                 s5pc1xx_phy_write_reg(0x2, OTG_PHYCTRL);
 339 #endif
 340         }
 341
 342         s5pc1xx_phy_write_reg(0x1, OTG_RSTCON);
 343         udelay(20);
 344         s5pc1xx_phy_write_reg(0x0, OTG_RSTCON);
 345         udelay(20);
 346 }
 347
 348 int s5p_usb_detect_irq(void)
 349 {
 350         u32 status;
 351         status = s5pc1xx_otg_read_reg(OTG_GINTSTS);
 352         return (status & 0x800c3810);
 353 }
 354
 355 void s5p_usb_clear_irq(void)
 356 {
 357         s5pc1xx_otg_write_reg(0xffffffff, OTG_GINTSTS);
 358 }
 359
 360 void s5p_usb_core_soft_reset(void)
 361 {
 362         u32 tmp;
 363
 364         s5pc1xx_otg_write_reg(CORE_SOFT_RESET, OTG_GRSTCTL);
 365
 366         do {
 367                 tmp = s5pc1xx_otg_read_reg(OTG_GRSTCTL);
 368         } while (!(tmp & AHB_MASTER_IDLE));
 369 }
 370
 371 void s5p_usb_wait_cable_insert(void)
 372 {
 373         u32 tmp;
 374         int ucFirst = 1;
 375
 376         do {
 377                 udelay(50);
 378
 379                 tmp = s5pc1xx_otg_read_reg(OTG_GOTGCTL);
 380
 381                 if (tmp & (B_SESSION_VALID | A_SESSION_VALID)) {
 382                         break;
 383                 } else if (ucFirst == 1) {
 384                         printf("Insert a OTG cable into the connector!\n");
 385                         ucFirst = 0;
 386                 }
 387         } while (1);
 388 }
 389
 390 void s5p_usb_init_core(void)
 391 {
 392         s5pc1xx_otg_write_reg(PTXFE_HALF | NPTXFE_HALF | MODE_SLAVE |
 393                         BURST_SINGLE | GBL_INT_UNMASK, OTG_GAHBCFG);
 394
 395         s5pc1xx_otg_write_reg(
 396                  0x0 << 15      /* PHY Low Power Clock sel */
 397                | 0x1 << 14      /* Non-Periodic TxFIFO Rewind Enable */
 398                | 0x5 << 10      /* Turnaround time */
 399                | 0x0 << 9       /* 0:HNP disable, 1:HNP enable */
 400                | 0x0 << 8       /* 0:SRP disable, 1:SRP enable */
 401                | 0x0 << 7       /* ULPI DDR sel */
 402                | 0x0 << 6       /* 0: high speed utmi+, 1: full speed serial */
 403                | 0x0 << 4       /* 0: utmi+, 1:ulpi */
 404                | 0x1 << 3       /* phy i/f  0:8bit, 1:16bit */
 405                | 0x7 << 0,      /* HS/FS Timeout* */
 406                OTG_GUSBCFG);
 407 }
 408
 409 void s5p_usb_check_current_mode(u8 *pucMode)
 410 {
 411         u32 tmp;
 412
 413         tmp = s5pc1xx_otg_read_reg(OTG_GINTSTS);
 414         *pucMode = tmp & 0x1;
 415 }
 416
 417 void s5p_usb_soft_disconnect(int set)
 418 {
 419         u32 tmp;
 420
 421         tmp = s5pc1xx_otg_read_reg(OTG_DCTL);
 422         if (set)
 423                 tmp |= SOFT_DISCONNECT;
 424         else
 425                 tmp &= ~SOFT_DISCONNECT;
 426         s5pc1xx_otg_write_reg(tmp, OTG_DCTL);
 427 }
 428
 429 void s5p_usb_init_device(void)
 430 {
 431         s5pc1xx_otg_write_reg(1 << 18 | otg.speed << 0, OTG_DCFG);
 432
 433         s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
 434                         INT_ENUMDONE | INT_RESET | INT_SUSPEND |
 435                         INT_RX_FIFO_NOT_EMPTY, OTG_GINTMSK);
 436 }
 437
 438 int s5p_usbctl_init(void)
 439 {
 440         u8 ucMode;
 441         u32 reg;
 442
 443         s5p_usb_init_base();
 444
 445         if (cpu_is_s5pc110()) {
 446                 reg = readl(S5PC110_USB_PHY_CON);
 447                 reg |= (1 << 0); /* USB PHY0 enable */
 448                 writel(reg, S5PC110_USB_PHY_CON);
 449         } else {
 450                 reg = readl(S5PC100_OTHERS);
 451                 reg |= (1 << 16); /* unmask usb signal */
 452                 writel(reg, S5PC100_OTHERS);
 453         }
 454
 455         otg.speed = speed;
 456         otg.set_config = 0;
 457         otg.ep0_state = EP0_STATE_INIT;
 458         otg.ep0_substate = 0;
 459
 460         s5p_usb_init_phy();
 461         s5p_usb_core_soft_reset();
 462         s5p_usb_wait_cable_insert();
 463         s5p_usb_init_core();
 464         s5p_usb_check_current_mode(&ucMode);
 465
 466         if (ucMode == INT_DEV_MODE) {
 467                 s5p_usb_soft_disconnect(1);
 468                 udelay(10);
 469                 s5p_usb_soft_disconnect(0);
 470                 s5p_usb_init_device();
 471                 return 0;
 472         } else {
 473                 printf("Error : Current Mode is Host\n");
 474                 return 0;
 475         }
 476 }
 477
 478 int s5p_usbc_activate(void)
 479 {
 480         return 0;
 481 }
 482
 483 void s5p_usb_stop(void)
 484 {
 485 }
 486
 487 void s5p_usb_set_inep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize)
 488 {
 489         if (type == EP_TYPE_CONTROL) {
 490                 s5pc1xx_otg_write_reg((pktcnt << 19) | (xfersize << 0),
 491                                 OTG_DIEPTSIZ0);
 492         } else if (type == EP_TYPE_BULK) {
 493                 s5pc1xx_otg_write_reg((1 << 29) | (pktcnt << 19) |
 494                                 (xfersize << 0), OTG_DIEPTSIZ_IN);
 495         }
 496 }
 497
 498 void s5p_usb_set_outep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize)
 499 {
 500         if (type == EP_TYPE_CONTROL) {
 501                 s5pc1xx_otg_write_reg((1 << 29) | (pktcnt << 19) |
 502                                 (xfersize << 0), OTG_DOEPTSIZ0);
 503         } else if (type == EP_TYPE_BULK) {
 504                 s5pc1xx_otg_write_reg((pktcnt << 19) | (xfersize << 0),
 505                                 OTG_DOEPTSIZ_OUT);
 506         }
 507 }
 508
 509 /* works on both aligned and unaligned buffers */
 510 void s5p_usb_write_ep0_fifo(u8 *buf, int num)
 511 {
 512         int i;
 513         u32 Wr_Data = 0;
 514
 515         for (i = 0; i < num; i += 4) {
 516                 Wr_Data = ((*(buf + 3)) << 24) |
 517                         ((*(buf + 2)) << 16) |
 518                         ((*(buf + 1)) << 8) |
 519                         *buf;
 520                 s5pc1xx_otg_write_reg(Wr_Data, OTG_EP0_FIFO);
 521                 buf += 4;
 522         }
 523 }
 524
 525 /* optimized fifo access routines, warning: only aligned buffers are supported */
 526 static inline void s5p_usb_write_in_fifo(u8 *buf, int num)
 527 {
 528         u32 fifo = otg_base + OTG_IN_FIFO;
 529         u32 *p = (u32 *)buf;
 530         int i;
 531
 532         for (i = 0; i < num; i += 4)
 533                 writel(*p++, fifo);
 534 }
 535
 536 static inline void s5p_usb_read_out_fifo(u8 *buf, int num)
 537 {
 538         u32 fifo = otg_base + OTG_OUT_FIFO;
 539         u32 *p = (u32 *)buf;
 540         int i;
 541
 542         for (i = 0; i < num; i += 4)
 543                 *p++ = readl(fifo);
 544 }
 545
 546 void s5p_usb_get_desc(void)
 547 {
 548         switch (otg.dev_req.wValue_H) {
 549         case DEVICE_DESCRIPTOR:
 550                 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
 551                                 otg.dev_req.wLength_L);
 552                 otg.ep0_state = EP0_STATE_GD_DEV_0;
 553                 break;
 554
 555         case CONFIGURATION_DESCRIPTOR:
 556                 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
 557                                 otg.dev_req.wLength_L);
 558
 559                 if (otg.req_length > CONFIG_DESC_SIZE)
 560                         otg.ep0_state = EP0_STATE_GD_CFG_0;
 561                 else
 562                         otg.ep0_state = EP0_STATE_GD_CFG_ONLY_0;
 563                 break;
 564
 565         case STRING_DESCRIPTOR:
 566                 switch (otg.dev_req.wValue_L) {
 567                 case 0:
 568                         otg.ep0_state = EP0_STATE_GD_STR_I0;
 569                         break;
 570                 case 1:
 571                         otg.ep0_state = EP0_STATE_GD_STR_I1;
 572                         break;
 573                 case 2:
 574                         otg.ep0_state = EP0_STATE_GD_STR_I2;
 575                         break;
 576                 default:
 577                         break;
 578                 }
 579                 break;
 580
 581         case ENDPOINT_DESCRIPTOR:
 582                 switch (otg.dev_req.wValue_L & 0xf) {
 583                 case 0:
 584                         otg.ep0_state = EP0_STATE_GD_EP0_ONLY_0;
 585                         break;
 586                 case 1:
 587                         otg.ep0_state = EP0_STATE_GD_EP1_ONLY_0;
 588                         break;
 589                 default:
 590                         break;
 591                 }
 592                 break;
 593
 594         case DEVICE_QUALIFIER:
 595                 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
 596                                 otg.dev_req.wLength_L);
 597                 otg.ep0_state = EP0_STATE_GD_DEV_QUALIFIER;
 598                 break;
 599
 600         case OTHER_SPEED_CONFIGURATION:
 601                 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
 602                                 otg.dev_req.wLength_L);
 603                 otg.ep0_state = EP0_STATE_GD_OTHER_SPEED;
 604                 break;
 605         }
 606 }
 607
 608 void s5p_usb_clear_feature(void)
 609 {
 610         switch (otg.dev_req.bmRequestType) {
 611         case DEVICE_RECIPIENT:
 612                 if (otg.dev_req.wValue_L == 1)
 613                         remode_wakeup = 0;
 614                 break;
 615
 616         case ENDPOINT_RECIPIENT:
 617                 if (otg.dev_req.wValue_L == 0) {
 618                         if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
 619                                 get_status.ep_ctrl = 0;
 620
 621                         /* IN Endpoint */
 622                         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
 623                                 get_status.ep_in = 0;
 624
 625                         /* OUT Endpoint */
 626                         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
 627                                 get_status.ep_out = 0;
 628                 }
 629                 break;
 630
 631         default:
 632                 break;
 633         }
 634         otg.ep0_state = EP0_STATE_INIT;
 635 }
 636
 637 void s5p_usb_set_feature(void)
 638 {
 639         switch (otg.dev_req.bmRequestType) {
 640         case DEVICE_RECIPIENT:
 641                 if (otg.dev_req.wValue_L == 1)
 642                         remode_wakeup = 1;
 643                 break;
 644
 645         case ENDPOINT_RECIPIENT:
 646                 if (otg.dev_req.wValue_L == 0) {
 647                         if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
 648                                 get_status.ep_ctrl = 1;
 649
 650                         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
 651                                 get_status.ep_in = 1;
 652
 653                         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
 654                                 get_status.ep_out = 1;
 655                 }
 656                 break;
 657
 658         default:
 659                 break;
 660         }
 661
 662         switch (otg.dev_req.wValue_L) {
 663         case EP_STALL:
 664                 /* TBD: additional processing if required */
 665                 break;
 666
 667         case TEST_MODE:
 668                 /* not support */
 669                 break;
 670
 671         default:
 672                 break;
 673         }
 674         otg.ep0_state = EP0_STATE_INIT;
 675 }
 676
 677 void s5p_usb_get_status(void)
 678 {
 679         switch (otg.dev_req.bmRequestType) {
 680         case (0x80):    /*device */
 681                 get_status.Device = ((u8) remode_wakeup << 1) | 0x1;
 682                 otg.ep0_state = EP0_STATE_GET_STATUS0;
 683                 break;
 684
 685         case (0x81):    /*interface */
 686                 get_status.Interface = 0;
 687                 otg.ep0_state = EP0_STATE_GET_STATUS1;
 688                 break;
 689
 690         case (0x82):    /*endpoint */
 691                 if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
 692                         otg.ep0_state = EP0_STATE_GET_STATUS2;
 693
 694                 if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
 695                         otg.ep0_state = EP0_STATE_GET_STATUS3;
 696
 697                 if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
 698                         otg.ep0_state = EP0_STATE_GET_STATUS4;
 699                 break;
 700
 701         default:
 702                 break;
 703         }
 704 }
 705
 706 void s5p_usb_ep0_int_hndlr(void)
 707 {
 708         u16 i;
 709         u32 buf[2] = {0x0000, };
 710         u16 addr;
 711
 712         if (otg.ep0_state == EP0_STATE_INIT) {
 713                 for (i = 0; i < 2; i++)
 714                         buf[i] = s5pc1xx_otg_read_reg(OTG_EP0_FIFO);
 715
 716                 otg.dev_req.bmRequestType = buf[0];
 717                 otg.dev_req.bRequest = buf[0] >> 8;
 718                 otg.dev_req.wValue_L = buf[0] >> 16;
 719                 otg.dev_req.wValue_H = buf[0] >> 24;
 720                 otg.dev_req.wIndex_L = buf[1];
 721                 otg.dev_req.wIndex_H = buf[1] >> 8;
 722                 otg.dev_req.wLength_L = buf[1] >> 16;
 723                 otg.dev_req.wLength_H = buf[1] >> 24;
 724
 725                 switch (otg.dev_req.bRequest) {
 726                 case STANDARD_SET_ADDRESS:
 727                         /* Set Address Update bit */
 728                         addr = (otg.dev_req.wValue_L);
 729                         s5pc1xx_otg_write_reg(1 << 18 | addr << 4 | otg.speed << 0,
 730                                OTG_DCFG);
 731                         otg.ep0_state = EP0_STATE_INIT;
 732                         break;
 733
 734                 case STANDARD_SET_DESCRIPTOR:
 735                         break;
 736
 737                 case STANDARD_SET_CONFIGURATION:
 738                         /* Configuration value in configuration descriptor */
 739                         config_value = otg.dev_req.wValue_L;
 740                         otg.set_config = 1;
 741                         otg.ep0_state = EP0_STATE_INIT;
 742
 743                         s5p_usb_connected = 1;
 744                         break;
 745
 746                 case STANDARD_GET_CONFIGURATION:
 747                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
 748
 749                         /*ep0 enable, clear nak, next ep0, 8byte */
 750                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 751                         s5pc1xx_otg_write_reg(config_value, OTG_EP0_FIFO);
 752                         otg.ep0_state = EP0_STATE_INIT;
 753                         break;
 754
 755                 case STANDARD_GET_DESCRIPTOR:
 756                         s5p_usb_get_desc();
 757                         break;
 758
 759                 case STANDARD_CLEAR_FEATURE:
 760                         s5p_usb_clear_feature();
 761                         break;
 762
 763                 case STANDARD_SET_FEATURE:
 764                         s5p_usb_set_feature();
 765                         break;
 766
 767                 case STANDARD_GET_STATUS:
 768                         s5p_usb_get_status();
 769                         break;
 770
 771                 case STANDARD_GET_INTERFACE:
 772                         otg.ep0_state = EP0_STATE_INTERFACE_GET;
 773                         break;
 774
 775                 case STANDARD_SET_INTERFACE:
 776                         get_intf.AlternateSetting = otg.dev_req.wValue_L;
 777                         otg.ep0_state = EP0_STATE_INIT;
 778                         break;
 779
 780                 case STANDARD_SYNCH_FRAME:
 781                         otg.ep0_state = EP0_STATE_INIT;
 782                         break;
 783
 784                 default:
 785                         break;
 786                 }
 787         }
 788
 789         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.ctrl_max_pktsize);
 790
 791         /*clear nak, next ep0, 64byte */
 792         s5pc1xx_otg_write_reg(((1 << 26) | (CONTROL_EP << 11) | (0 << 0)),
 793                         OTG_DIEPCTL0);
 794 }
 795
 796 void s5p_usb_set_otherspeed_conf_desc(u32 length)
 797 {
 798         /* Standard device descriptor */
 799         if (length == 9) {
 800                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 9);
 801                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 802                 s5p_usb_write_ep0_fifo((u8 *) &config_full, 9);
 803         } else if (length == 32) {
 804                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 32);
 805                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 806                 s5p_usb_write_ep0_fifo((u8 *) &config_full_total, 32);
 807         }
 808         otg.ep0_state = EP0_STATE_INIT;
 809 }
 810
 811 void s5p_usb_transfer_ep0(void)
 812 {
 813         switch (otg.ep0_state) {
 814         case EP0_STATE_INIT:
 815                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 0);
 816
 817                 /*ep0 enable, clear nak, next ep0, 8byte */
 818                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 819                 break;
 820
 821         case EP0_STATE_GD_DEV_0:
 822                 /*ep0 enable, clear nak, next ep0, max 64byte */
 823                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 824                 if (otg.req_length < DEVICE_DESC_SIZE) {
 825                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 826                                         otg.req_length);
 827                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)),
 828                                         otg.req_length);
 829                 } else {
 830                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 831                                         DEVICE_DESC_SIZE);
 832                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)),
 833                                         DEVICE_DESC_SIZE);
 834                 }
 835                 otg.ep0_state = EP0_STATE_INIT;
 836                 break;
 837
 838         case EP0_STATE_GD_DEV_1:
 839                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 840                 if (otg.req_length < (2 * FS_CTRL_PKT_SIZE)) {
 841                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
 842                                         FS_CTRL_PKT_SIZE,
 843                                         otg.req_length - FS_CTRL_PKT_SIZE);
 844                         otg.ep0_state = EP0_STATE_INIT;
 845                 } else {
 846                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
 847                                         FS_CTRL_PKT_SIZE, FS_CTRL_PKT_SIZE);
 848                         otg.ep0_state = EP0_STATE_GD_DEV_2;
 849                 }
 850                 break;
 851
 852         case EP0_STATE_GD_DEV_2:
 853                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 854                 if (otg.req_length < DEVICE_DESC_SIZE) {
 855                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
 856                                         (2 * FS_CTRL_PKT_SIZE),
 857                                         otg.req_length - 2 * FS_CTRL_PKT_SIZE);
 858                 } else {
 859                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
 860                                         (2 * FS_CTRL_PKT_SIZE),
 861                                         DEVICE_DESC_SIZE - 2 * FS_CTRL_PKT_SIZE);
 862                 }
 863                 otg.ep0_state = EP0_STATE_INIT;
 864                 break;
 865
 866         case EP0_STATE_GD_CFG_0:
 867                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 868                 if (otg.req_length < CONFIG_DESC_TOTAL_SIZE) {
 869                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 870                                         otg.req_length);
 871                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
 872                                         otg.req_length);
 873                 } else {
 874                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 875                                         CONFIG_DESC_TOTAL_SIZE);
 876                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
 877                                         CONFIG_DESC_TOTAL_SIZE);
 878                 }
 879                 otg.ep0_state = EP0_STATE_INIT;
 880                 break;
 881
 882         case EP0_STATE_GD_CFG_1:
 883                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 884                 if (otg.req_length < (2 * FS_CTRL_PKT_SIZE)) {
 885                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 886                                         FS_CTRL_PKT_SIZE,
 887                                         (otg.req_length - FS_CTRL_PKT_SIZE));
 888                         otg.ep0_state = EP0_STATE_INIT;
 889                 } else {
 890                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 891                                         FS_CTRL_PKT_SIZE, FS_CTRL_PKT_SIZE);
 892                         otg.ep0_state = EP0_STATE_GD_CFG_2;
 893                 }
 894                 break;
 895
 896         case EP0_STATE_GD_CFG_2:
 897                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 898                 if (otg.req_length < (3 * FS_CTRL_PKT_SIZE)) {
 899                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 900                                         (2 * FS_CTRL_PKT_SIZE),
 901                                         otg.req_length - 2 * FS_CTRL_PKT_SIZE);
 902                         otg.ep0_state = EP0_STATE_INIT;
 903                 } else {
 904                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 905                                         (2 * FS_CTRL_PKT_SIZE), FS_CTRL_PKT_SIZE);
 906                         otg.ep0_state = EP0_STATE_GD_CFG_3;
 907                 }
 908                 break;
 909
 910         case EP0_STATE_GD_CFG_3:
 911                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 912                 if (otg.req_length < (4 * FS_CTRL_PKT_SIZE)) {
 913                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 914                                         (3 * FS_CTRL_PKT_SIZE),
 915                                         otg.req_length - 3 * FS_CTRL_PKT_SIZE);
 916                         otg.ep0_state = EP0_STATE_INIT;
 917                 } else {
 918                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 919                                         (3 * FS_CTRL_PKT_SIZE), FS_CTRL_PKT_SIZE);
 920                         otg.ep0_state = EP0_STATE_GD_CFG_4;
 921                 }
 922                 break;
 923
 924         case EP0_STATE_GD_CFG_4:
 925                 otg.ep0_state = EP0_STATE_INIT;
 926                 break;
 927
 928         case EP0_STATE_GD_DEV_QUALIFIER:
 929                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 930                 if (otg.req_length < 10) {
 931                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 932                                         otg.req_length);
 933                         s5p_usb_write_ep0_fifo((u8 *)qualifier_desc,
 934                                         otg.req_length);
 935                 } else {
 936                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 10);
 937                         s5p_usb_write_ep0_fifo((u8 *)qualifier_desc, 10);
 938                 }
 939                 otg.ep0_state = EP0_STATE_INIT;
 940                 break;
 941
 942         case EP0_STATE_GD_OTHER_SPEED:
 943                 s5p_usb_set_otherspeed_conf_desc(otg.req_length);
 944                 break;
 945
 946         case EP0_STATE_GD_OTHER_SPEED_HIGH_1:
 947                 if (otg.req_length == 9) {
 948                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
 949                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 950                         s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 8, 1);
 951                         otg.ep0_state = EP0_STATE_INIT;
 952                 } else {
 953                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
 954                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 955                         s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 8, 8);
 956                         otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_2;
 957                 }
 958                 break;
 959
 960         case EP0_STATE_GD_OTHER_SPEED_HIGH_2:
 961                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
 962                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 963                 s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 16, 8);
 964                 otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_3;
 965                 break;
 966
 967         case EP0_STATE_GD_OTHER_SPEED_HIGH_3:
 968                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
 969                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 970                 s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 24, 8);
 971                 otg.ep0_state = EP0_STATE_INIT;
 972                 break;
 973
 974         case EP0_STATE_GD_CFG_ONLY_0:
 975                 if (otg.req_length < CONFIG_DESC_SIZE) {
 976                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 977                                         otg.req_length);
 978                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 979                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
 980                                         otg.req_length);
 981                 } else {
 982                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 983                                         CONFIG_DESC_SIZE);
 984                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 985                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
 986                                         CONFIG_DESC_SIZE);
 987                 }
 988                 otg.ep0_state = EP0_STATE_INIT;
 989                 break;
 990
 991         case EP0_STATE_GD_CFG_ONLY_1:
 992                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 993                 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 994                                 FS_CTRL_PKT_SIZE,
 995                                 CONFIG_DESC_SIZE - FS_CTRL_PKT_SIZE);
 996                 otg.ep0_state = EP0_STATE_INIT;
 997                 break;
 998
 999         case EP0_STATE_GD_IF_ONLY_0:
1000                 if (otg.req_length < INTERFACE_DESC_SIZE) {
1001                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
1002                                         otg.req_length);
1003                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1004                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.intf)),
1005                                         otg.req_length);
1006                 } else {
1007                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
1008                                         INTERFACE_DESC_SIZE);
1009                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1010                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.intf)),
1011                                         INTERFACE_DESC_SIZE);
1012                 }
1013                 otg.ep0_state = EP0_STATE_INIT;
1014                 break;
1015
1016         case EP0_STATE_GD_IF_ONLY_1:
1017                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1018                 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.intf)) +
1019                                 FS_CTRL_PKT_SIZE,
1020                                 INTERFACE_DESC_SIZE - FS_CTRL_PKT_SIZE);
1021                 otg.ep0_state = EP0_STATE_INIT;
1022                 break;
1023
1024         case EP0_STATE_GD_EP0_ONLY_0:
1025                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1026                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, ENDPOINT_DESC_SIZE);
1027                 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.ep1)),
1028                                 ENDPOINT_DESC_SIZE);
1029                 otg.ep0_state = EP0_STATE_INIT;
1030                 break;
1031
1032         case EP0_STATE_GD_EP1_ONLY_0:
1033                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, ENDPOINT_DESC_SIZE);
1034                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1035                 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.ep2)),
1036                                 ENDPOINT_DESC_SIZE);
1037                 otg.ep0_state = EP0_STATE_INIT;
1038                 break;
1039
1040         case EP0_STATE_GD_STR_I0:
1041                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, STRING_DESC0_SIZE);
1042                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1043                 s5p_usb_write_ep0_fifo((u8 *)string_desc0, STRING_DESC0_SIZE);
1044                 otg.ep0_state = EP0_STATE_INIT;
1045                 break;
1046
1047         case EP0_STATE_GD_STR_I1:
1048                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, sizeof(string_desc1));
1049                 if ((otg.ep0_substate * otg.ctrl_max_pktsize +
1050                         otg.ctrl_max_pktsize) < sizeof(string_desc1)) {
1051                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1052
1053                         s5p_usb_write_ep0_fifo((u8 *)string_desc1 +
1054                                         (otg.ep0_substate * otg.ctrl_max_pktsize),
1055                                         otg.ctrl_max_pktsize);
1056                         otg.ep0_state = EP0_STATE_GD_STR_I1;
1057                         otg.ep0_substate++;
1058                 } else {
1059                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1060
1061                         s5p_usb_write_ep0_fifo((u8 *)string_desc1 +
1062                                         (otg.ep0_substate * otg.ctrl_max_pktsize),
1063                                         sizeof(string_desc1) - (otg.ep0_substate *
1064                                                 otg.ctrl_max_pktsize));
1065                         otg.ep0_state = EP0_STATE_INIT;
1066                         otg.ep0_substate = 0;
1067                 }
1068                 break;
1069
1070         case EP0_STATE_GD_STR_I2:
1071                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, sizeof(string_desc2));
1072                 if ((otg.ep0_substate * otg.ctrl_max_pktsize +
1073                         otg.ctrl_max_pktsize) < sizeof(string_desc2)) {
1074                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1075
1076                         s5p_usb_write_ep0_fifo((u8 *) string_desc2 +
1077                                         (otg.ep0_substate * otg.ctrl_max_pktsize),
1078                                         otg.ctrl_max_pktsize);
1079                         otg.ep0_state = EP0_STATE_GD_STR_I2;
1080                         otg.ep0_substate++;
1081                 } else {
1082                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1083                         s5p_usb_write_ep0_fifo((u8 *) string_desc2 +
1084                                         (otg.ep0_substate * otg.ctrl_max_pktsize),
1085                                         sizeof(string_desc2) - (otg.ep0_substate *
1086                                                 otg.ctrl_max_pktsize));
1087                         otg.ep0_state = EP0_STATE_INIT;
1088                         otg.ep0_substate = 0;
1089                 }
1090                 break;
1091
1092         case EP0_STATE_INTERFACE_GET:
1093                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1094                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1095                 s5p_usb_write_ep0_fifo((u8 *) &get_intf, 1);
1096                 otg.ep0_state = EP0_STATE_INIT;
1097                 break;
1098
1099         case EP0_STATE_GET_STATUS0:
1100                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1101                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1102                 s5p_usb_write_ep0_fifo((u8 *) &get_status, 1);
1103                 otg.ep0_state = EP0_STATE_INIT;
1104                 break;
1105
1106         case EP0_STATE_GET_STATUS1:
1107                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1108                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1109                 s5p_usb_write_ep0_fifo((u8 *) &get_status + 1, 1);
1110                 otg.ep0_state = EP0_STATE_INIT;
1111                 break;
1112
1113         case EP0_STATE_GET_STATUS2:
1114                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1115                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1116                 s5p_usb_write_ep0_fifo((u8 *) &get_status + 2, 1);
1117                 otg.ep0_state = EP0_STATE_INIT;
1118                 break;
1119
1120         case EP0_STATE_GET_STATUS3:
1121                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1122                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1123                 s5p_usb_write_ep0_fifo((u8 *) &get_status + 3, 1);
1124                 otg.ep0_state = EP0_STATE_INIT;
1125                 break;
1126
1127         case EP0_STATE_GET_STATUS4:
1128                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1129                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1130                 s5p_usb_write_ep0_fifo((u8 *) &get_status + 4, 1);
1131                 otg.ep0_state = EP0_STATE_INIT;
1132                 break;
1133
1134         default:
1135                 break;
1136         }
1137 }
1138
1139 void s5p_usb_tx(char *tx_data, int tx_size)
1140 {
1141         otg.up_ptr = (u8 *) tx_data;
1142         otg.up_addr = (u32) tx_data;
1143         otg.up_size = tx_size;
1144
1145         if (otg.op_mode == USB_CPU) {
1146                 if (otg.up_size > otg.bulkin_max_pktsize) {
1147                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1,
1148                                         otg.bulkin_max_pktsize);
1149                 } else {
1150                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1, otg.up_size);
1151                 }
1152
1153                 /*ep1 enable, clear nak, bulk, usb active, max pkt */
1154                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1155                                 otg.bulkin_max_pktsize << 0, OTG_DIEPCTL_IN);
1156
1157                 s5p_usb_write_in_fifo(otg.up_ptr, otg.up_size);
1158         } else if ((otg.op_mode == USB_DMA) && (otg.up_size > 0)) {
1159                 u32 pktcnt, remainder;
1160
1161                 s5pc1xx_otg_write_reg(MODE_DMA | BURST_INCR4 | GBL_INT_UNMASK,
1162                                 OTG_GAHBCFG);
1163                 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1164                                 INT_ENUMDONE | INT_RESET | INT_SUSPEND,
1165                                 OTG_GINTMSK);
1166
1167                 s5pc1xx_otg_write_reg((u32) otg.up_ptr, OTG_DIEPDMA_IN);
1168
1169                 pktcnt = (u32) (otg.up_size / otg.bulkin_max_pktsize);
1170                 remainder = (u32) (otg.up_size % otg.bulkin_max_pktsize);
1171                 if (remainder != 0)
1172                         pktcnt += 1;
1173
1174                 if (pktcnt > 1023) {
1175                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1023,
1176                                         otg.bulkin_max_pktsize * 1023);
1177                 } else {
1178                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt,
1179                                         otg.up_size);
1180                 }
1181
1182                 /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */
1183                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1184                                 BULK_IN_EP << 11 | otg.bulkin_max_pktsize << 0,
1185                                 OTG_DIEPCTL_IN);
1186         }
1187 }
1188
1189 void s5p_usb_rx(u32 fifo_cnt_byte)
1190 {
1191         if (otg.op_mode == USB_CPU) {
1192                 s5p_usb_read_out_fifo((u8 *)otg.dn_ptr, fifo_cnt_byte);
1193                 otg.dn_ptr += fifo_cnt_byte;
1194
1195                 s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1,
1196                                 otg.bulkout_max_pktsize);
1197
1198                 /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt */
1199                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1200                                 otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1201
1202                 if (((u32)otg.dn_ptr - otg.dn_addr) >= (otg.dn_filesize))
1203                         s5p_receive_done = 1;
1204         } else if (otg.dn_filesize > otg.bulkout_max_pktsize) {
1205                 u32 pkt_cnt, remain_cnt;
1206
1207                 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1208                                 INT_ENUMDONE | INT_RESET | INT_SUSPEND,
1209                                 OTG_GINTMSK);
1210                 s5pc1xx_otg_write_reg(MODE_DMA | BURST_INCR4 | GBL_INT_UNMASK,
1211                                 OTG_GAHBCFG);
1212                 s5pc1xx_otg_write_reg((u32) otg.dn_ptr, OTG_DOEPDMA_OUT);
1213                 pkt_cnt = (u32)(otg.dn_filesize - otg.bulkout_max_pktsize) /
1214                                 otg.bulkout_max_pktsize;
1215                 remain_cnt = (u32)((otg.dn_filesize - otg.bulkout_max_pktsize) %
1216                                 otg.bulkout_max_pktsize);
1217
1218                 if (remain_cnt != 0)
1219                         pkt_cnt += 1;
1220
1221                 if (pkt_cnt > 1023) {
1222                         s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1023,
1223                                         otg.bulkout_max_pktsize * 1023);
1224                 } else {
1225                         s5p_usb_set_outep_xfersize(EP_TYPE_BULK, pkt_cnt,
1226                                         otg.dn_filesize - otg.bulkout_max_pktsize);
1227                 }
1228
1229                 /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt */
1230                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1231                                 otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1232         }
1233 }
1234
1235 void s5p_usb_int_bulkout(u32 fifo_cnt_byte)
1236 {
1237         s5p_usb_rx(fifo_cnt_byte);
1238 }
1239
1240 void s5p_usb_dma_in_done(void)
1241 {
1242         s32 remain_cnt;
1243
1244         otg.up_ptr = (u8 *)s5pc1xx_otg_read_reg(OTG_DIEPDMA_IN);
1245         remain_cnt = otg.up_size - ((u32) otg.up_ptr - otg.up_addr);
1246
1247         if (remain_cnt > 0) {
1248                 u32 pktcnt, remainder;
1249                 pktcnt = (u32)(remain_cnt / otg.bulkin_max_pktsize);
1250                 remainder = (u32)(remain_cnt % otg.bulkin_max_pktsize);
1251
1252                 if (remainder != 0)
1253                         pktcnt += 1;
1254
1255                 if (pktcnt > 1023) {
1256                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1023,
1257                                         otg.bulkin_max_pktsize * 1023);
1258                 } else {
1259                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt,
1260                                         remain_cnt);
1261                 }
1262
1263                 /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */
1264                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1265                                 BULK_IN_EP << 11 | otg.bulkin_max_pktsize << 0,
1266                                 OTG_DIEPCTL_IN);
1267
1268                 s5p_receive_done = 1;
1269         }
1270 }
1271
1272 void s5p_usb_dma_out_done(void)
1273 {
1274         s32 remain_cnt;
1275
1276         otg.dn_ptr = (u8 *)s5pc1xx_otg_read_reg(OTG_DOEPDMA_OUT);
1277
1278         remain_cnt = otg.dn_filesize - ((u32) otg.dn_ptr - otg.dn_addr + 8);
1279
1280         if (remain_cnt > 0) {
1281                 u32 pktcnt, remainder;
1282                 pktcnt = (u32)(remain_cnt / otg.bulkout_max_pktsize);
1283                 remainder = (u32)(remain_cnt % otg.bulkout_max_pktsize);
1284
1285                 if (remainder != 0)
1286                         pktcnt += 1;
1287
1288                 if (pktcnt > 1023) {
1289                         s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1023,
1290                                         otg.bulkout_max_pktsize * 1023);
1291                 } else {
1292                         s5p_usb_set_outep_xfersize(EP_TYPE_BULK, pktcnt,
1293                                         remain_cnt);
1294                 }
1295
1296                 /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64 */
1297                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1298                                 otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1299         } else {
1300                 udelay(500);    /*for FPGA ??? */
1301         }
1302 }
1303
1304 void s5p_usb_set_all_outep_nak(void)
1305 {
1306         u8 i;
1307         u32 tmp;
1308
1309         for (i = 0; i < 16; i++) {
1310                 tmp = s5pc1xx_otg_read_reg(OTG_DOEPCTL0 + 0x20 * i);
1311                 tmp |= DEPCTL_SNAK;
1312                 s5pc1xx_otg_write_reg(tmp, OTG_DOEPCTL0 + 0x20 * i);
1313         }
1314 }
1315
1316 void s5p_usb_clear_all_outep_nak(void)
1317 {
1318         u8 i;
1319         u32 tmp;
1320
1321         for (i = 0; i < 16; i++) {
1322                 tmp = s5pc1xx_otg_read_reg(OTG_DOEPCTL0 + 0x20 * i);
1323                 tmp |= (DEPCTL_EPENA | DEPCTL_CNAK);
1324                 s5pc1xx_otg_write_reg(tmp, OTG_DOEPCTL0 + 0x20 * i);
1325         }
1326 }
1327
1328 void s5p_usb_set_max_pktsize(USB_SPEED speed)
1329 {
1330         otg.speed = USB_HIGH;
1331         otg.ctrl_max_pktsize = HS_CTRL_PKT_SIZE;
1332         otg.bulkin_max_pktsize = HS_BULK_PKT_SIZE;
1333         otg.bulkout_max_pktsize = HS_BULK_PKT_SIZE;
1334 }
1335
1336 void s5p_usb_set_endpoint(void)
1337 {
1338         /* Unmask OTG_DAINT source */
1339         s5pc1xx_otg_write_reg(0xff, OTG_DIEPINT0);
1340         s5pc1xx_otg_write_reg(0xff, OTG_DOEPINT0);
1341         s5pc1xx_otg_write_reg(0xff, OTG_DIEPINT_IN);
1342         s5pc1xx_otg_write_reg(0xff, OTG_DOEPINT_OUT);
1343
1344         /* Init For Ep0 */
1345         /*MPS:64bytes */
1346         s5pc1xx_otg_write_reg(((1 << 26) | (CONTROL_EP << 11) | (0 << 0)),
1347                         OTG_DIEPCTL0);
1348         /*ep0 enable, clear nak */
1349         s5pc1xx_otg_write_reg((1u << 31) | (1 << 26) | (0 << 0),
1350                         OTG_DOEPCTL0);
1351 }
1352
1353 void s5p_usb_set_descriptors(void)
1354 {
1355 #if defined (CONFIG_SAMSUNG_USB)
1356         otg.desc.dev.bLength            = DEVICE_DESC_SIZE;
1357         otg.desc.dev.bDescriptorType    = DEVICE_DESCRIPTOR;
1358         otg.desc.dev.bDeviceClass       = 0xFF;
1359         otg.desc.dev.bDeviceSubClass    = 0x0;
1360         otg.desc.dev.bDeviceProtocol    = 0x0;
1361         otg.desc.dev.bMaxPacketSize0    = otg.ctrl_max_pktsize;
1362         otg.desc.dev.idVendorL          = 0xE8;
1363         otg.desc.dev.idVendorH          = 0x04;
1364         otg.desc.dev.idProductL         = 0x04;
1365         otg.desc.dev.idProductH         = 0x12;
1366         otg.desc.dev.iManufacturer      = 0x0;
1367         otg.desc.dev.iProduct           = 0x2;
1368         otg.desc.dev.iSerialNumber      = 0x0;
1369         otg.desc.dev.bNumConfigurations = 0x1;
1370         otg.desc.dev.bcdUSBL    = 0x00;
1371         otg.desc.dev.bcdUSBH    = 0x02;
1372
1373         otg.desc.config.bLength         = CONFIG_DESC_SIZE;
1374         otg.desc.config.bDescriptorType = CONFIGURATION_DESCRIPTOR;
1375         otg.desc.config.wTotalLengthL   = CONFIG_DESC_TOTAL_SIZE;
1376         otg.desc.config.wTotalLengthH   = 0;
1377         otg.desc.config.bNumInterfaces  = 1;
1378         otg.desc.config.bConfigurationValue = 1;
1379         otg.desc.config.iConfiguration  = 0;
1380         otg.desc.config.bmAttributes    = CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED;
1381         otg.desc.config.maxPower        = 50;
1382 #else
1383         otg.desc.dev.bLength            = DEVICE_DESC_SIZE;
1384         otg.desc.dev.bDescriptorType    = DEVICE_DESCRIPTOR;
1385         otg.desc.dev.bDeviceClass       = 0xFF;
1386         otg.desc.dev.bDeviceSubClass    = 0x0;
1387         otg.desc.dev.bDeviceProtocol    = 0x0;
1388         otg.desc.dev.bMaxPacketSize0    = otg.ctrl_max_pktsize;
1389         otg.desc.dev.idVendorL          = 0xE8;
1390         otg.desc.dev.idVendorH          = 0x04;
1391         otg.desc.dev.idProductL         = 0x34;
1392         otg.desc.dev.idProductH         = 0x12;
1393         otg.desc.dev.bcdDeviceL         = 0x00;
1394         otg.desc.dev.bcdDeviceH         = 0x01;
1395         otg.desc.dev.iManufacturer      = 0x1;
1396         otg.desc.dev.iProduct           = 0x2;
1397         otg.desc.dev.iSerialNumber      = 0x0;
1398         otg.desc.dev.bNumConfigurations = 0x1;
1399         otg.desc.dev.bcdUSBL    = 0x00;
1400         otg.desc.dev.bcdUSBH    = 0x02;
1401
1402         otg.desc.config.bLength         = CONFIG_DESC_SIZE;
1403         otg.desc.config.bDescriptorType = CONFIGURATION_DESCRIPTOR;
1404         otg.desc.config.wTotalLengthL   = CONFIG_DESC_TOTAL_SIZE;
1405         otg.desc.config.wTotalLengthH   = 0;
1406         otg.desc.config.bNumInterfaces  = 1;
1407         otg.desc.config.bConfigurationValue = 1;
1408         otg.desc.config.iConfiguration  = 0;
1409         otg.desc.config.bmAttributes    = CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED;
1410         otg.desc.config.maxPower        = 25;
1411 #endif
1412         otg.desc.intf.bLength           = INTERFACE_DESC_SIZE;
1413         otg.desc.intf.bDescriptorType   = INTERFACE_DESCRIPTOR;
1414         otg.desc.intf.bInterfaceNumber  = 0x0;
1415         otg.desc.intf.bAlternateSetting = 0x0;
1416         otg.desc.intf.bNumEndpoints     = 2;
1417         otg.desc.intf.bInterfaceClass   = 0xff;
1418         otg.desc.intf.bInterfaceSubClass = 0xff;
1419         otg.desc.intf.bInterfaceProtocol = 0xff;
1420         otg.desc.intf.iInterface        = 0x0;
1421
1422         otg.desc.ep1.bLength            = ENDPOINT_DESC_SIZE;
1423         otg.desc.ep1.bDescriptorType    = ENDPOINT_DESCRIPTOR;
1424         otg.desc.ep1.bEndpointAddress   = BULK_IN_EP | EP_ADDR_IN;
1425         otg.desc.ep1.bmAttributes       = EP_ATTR_BULK;
1426         otg.desc.ep1.wMaxPacketSizeL    = (u8)otg.bulkin_max_pktsize;
1427         otg.desc.ep1.wMaxPacketSizeH    = (u8)(otg.bulkin_max_pktsize >> 8);
1428         otg.desc.ep1.bInterval          = 0x0;
1429
1430         otg.desc.ep2.bLength            = ENDPOINT_DESC_SIZE;
1431         otg.desc.ep2.bDescriptorType    = ENDPOINT_DESCRIPTOR;
1432         otg.desc.ep2.bEndpointAddress   = BULK_OUT_EP | EP_ADDR_OUT;
1433         otg.desc.ep2.bmAttributes       = EP_ATTR_BULK;
1434         otg.desc.ep2.wMaxPacketSizeL    = (u8)otg.bulkout_max_pktsize;
1435         otg.desc.ep2.wMaxPacketSizeH    = (u8)(otg.bulkout_max_pktsize >> 8);
1436         otg.desc.ep2.bInterval          = 0x0;
1437 }
1438
1439 void s5p_usb_check_speed(USB_SPEED *speed)
1440 {
1441         u32 status;
1442
1443         status = s5pc1xx_otg_read_reg(OTG_DSTS);
1444
1445         *speed = (USB_SPEED)((status & 0x6) >> 1);
1446 }
1447
1448 int s5p_usb_check_setconf(void)
1449 {
1450         return otg.set_config;
1451 }
1452
1453 void s5p_usb_set_opmode(USB_OPMODE mode)
1454 {
1455         otg.op_mode = mode;
1456
1457         s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP | INT_ENUMDONE |
1458                         INT_RESET | INT_SUSPEND | INT_RX_FIFO_NOT_EMPTY,
1459                         OTG_GINTMSK);
1460
1461         s5pc1xx_otg_write_reg(MODE_SLAVE | BURST_SINGLE | GBL_INT_UNMASK,
1462                         OTG_GAHBCFG);
1463
1464         s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1, otg.bulkout_max_pktsize);
1465         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1, 0);
1466
1467         /*bulk out ep enable, clear nak, bulk, usb active, next ep3, max pkt */
1468         s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1469                         otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1470
1471         /*bulk in ep enable, clear nak, bulk, usb active, next ep1, max pkt */
1472         s5pc1xx_otg_write_reg(0u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1473                         otg.bulkin_max_pktsize << 0, OTG_DIEPCTL_IN);
1474 }
1475
1476 void s5p_usb_reset(void)
1477 {
1478         s5p_usb_set_all_outep_nak();
1479
1480         otg.ep0_state = EP0_STATE_INIT;
1481         s5pc1xx_otg_write_reg(((1 << BULK_OUT_EP) | (1 << CONTROL_EP)) << 16 |
1482                         ((1 << BULK_IN_EP) | (1 << CONTROL_EP)), OTG_DAINTMSK);
1483         s5pc1xx_otg_write_reg(CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR |
1484                         TRANSFER_DONE, OTG_DOEPMSK);
1485         s5pc1xx_otg_write_reg(INTKN_TXFEMP | NON_ISO_IN_EP_TIMEOUT | AHB_ERROR |
1486                         TRANSFER_DONE, OTG_DIEPMSK);
1487
1488         /* Rx FIFO Size */
1489         s5pc1xx_otg_write_reg(RX_FIFO_SIZE, OTG_GRXFSIZ);
1490
1491         /* Non Periodic Tx FIFO Size */
1492         s5pc1xx_otg_write_reg(NPTX_FIFO_SIZE << 16 | NPTX_FIFO_START_ADDR << 0,
1493                         OTG_GNPTXFSIZ);
1494
1495         s5p_usb_clear_all_outep_nak();
1496
1497         /*clear device address */
1498         s5pc1xx_otg_write_reg(s5pc1xx_otg_read_reg(OTG_DCFG) & ~(0x7f << 4),
1499                         OTG_DCFG);
1500
1501         if (SUSPEND_RESUME_ON) {
1502                 s5pc1xx_otg_write_reg(s5pc1xx_otg_read_reg(OTG_PCGCCTRL) & ~(1 << 0),
1503                                 OTG_PCGCCTRL);
1504         }
1505 }
1506
1507 int s5p_usb_set_init(void)
1508 {
1509         u32 status;
1510
1511         status = s5pc1xx_otg_read_reg(OTG_DSTS);
1512
1513         /* Set if Device is High speed or Full speed */
1514         if (((status & 0x6) >> 1) == USB_HIGH) {
1515                 s5p_usb_set_max_pktsize(USB_HIGH);
1516         } else if (((status & 0x6) >> 1) == USB_FULL) {
1517                 printf("Error: Don't support Full_Speed\n");
1518                 return 0;
1519         } else {
1520                 printf("Error: Neither High_Speed nor Full_Speed\n");
1521                 return 0;
1522         }
1523
1524         s5p_usb_set_endpoint();
1525         s5p_usb_set_descriptors();
1526         s5p_usb_set_opmode(op_mode);
1527
1528         return 1;
1529 }
1530
1531 void s5p_usb_pkt_receive(void)
1532 {
1533         u32 rx_status;
1534         u32 fifo_cnt_byte;
1535
1536         rx_status = s5pc1xx_otg_read_reg(OTG_GRXSTSP);
1537
1538         if ((rx_status & (0xf << 17)) == SETUP_PKT_RECEIVED) {
1539                 s5p_usb_ep0_int_hndlr();
1540         } else if ((rx_status & (0xf << 17)) == OUT_PKT_RECEIVED) {
1541                 fifo_cnt_byte = (rx_status & 0x7ff0) >> 4;
1542
1543                 if ((rx_status & BULK_OUT_EP) && (fifo_cnt_byte)) {
1544                         s5p_usb_int_bulkout(fifo_cnt_byte);
1545                         if (otg.op_mode == USB_CPU) {
1546                                 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP |
1547                                         INT_IN_EP | INT_ENUMDONE | INT_RESET |
1548                                         INT_SUSPEND | INT_RX_FIFO_NOT_EMPTY,
1549                                         OTG_GINTMSK);
1550                         }
1551                         return;
1552                 }
1553
1554         } else if ((rx_status & (0xf << 17)) == GLOBAL_OUT_NAK) {
1555                 /* nop */
1556         } else if ((rx_status & (0xf << 17)) == OUT_TRNASFER_COMPLETED) {
1557                 /* nop */
1558         } else if ((rx_status & (0xf << 17)) == SETUP_TRANSACTION_COMPLETED) {
1559                 /* nop */
1560         } else {
1561                 /* nop */
1562         }
1563 }
1564
1565 void s5p_usb_transfer(void)
1566 {
1567         u32 ep_int;
1568         u32 check_dma;
1569         u32 ep_int_status;
1570
1571         ep_int = s5pc1xx_otg_read_reg(OTG_DAINT);
1572
1573         if (ep_int & (1 << CONTROL_EP)) {
1574                 ep_int_status = s5pc1xx_otg_read_reg(OTG_DIEPINT0);
1575
1576                 if (ep_int_status & INTKN_TXFEMP) {
1577                         u32 uNTxFifoSpace;
1578                         do {
1579                                 uNTxFifoSpace = s5pc1xx_otg_read_reg(OTG_GNPTXSTS)
1580                                                 & 0xffff;
1581                         } while (uNTxFifoSpace < otg.ctrl_max_pktsize);
1582
1583                         s5p_usb_transfer_ep0();
1584                 }
1585
1586                 s5pc1xx_otg_write_reg(ep_int_status, OTG_DIEPINT0);
1587         }
1588
1589         if (ep_int & ((1 << CONTROL_EP) << 16)) {
1590                 ep_int_status = s5pc1xx_otg_read_reg(OTG_DOEPINT0);
1591
1592                 s5p_usb_set_outep_xfersize(EP_TYPE_CONTROL, 1, 8);
1593                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26, OTG_DOEPCTL0);
1594
1595                 s5pc1xx_otg_write_reg(ep_int_status, OTG_DOEPINT0);
1596         }
1597
1598         if (ep_int & (1 << BULK_IN_EP)) {
1599                 ep_int_status = s5pc1xx_otg_read_reg(OTG_DIEPINT_IN);
1600
1601                 s5pc1xx_otg_write_reg(ep_int_status, OTG_DIEPINT_IN);
1602                 check_dma = s5pc1xx_otg_read_reg(OTG_GAHBCFG);
1603
1604                 if ((check_dma & MODE_DMA) && (ep_int_status & TRANSFER_DONE))
1605                         s5p_usb_dma_in_done();
1606         }
1607
1608         if (ep_int & ((1 << BULK_OUT_EP) << 16)) {
1609                 ep_int_status = s5pc1xx_otg_read_reg(OTG_DOEPINT_OUT);
1610
1611                 s5pc1xx_otg_write_reg(ep_int_status, OTG_DOEPINT_OUT);
1612                 check_dma = s5pc1xx_otg_read_reg(OTG_GAHBCFG);
1613
1614                 if ((check_dma & MODE_DMA) && (ep_int_status & TRANSFER_DONE))
1615                         s5p_usb_dma_out_done();
1616         }
1617 }
1618
1619 void s5p_udc_int_hndlr(void)
1620 {
1621         u32 int_status;
1622         int tmp;
1623
1624         int_status = s5pc1xx_otg_read_reg(OTG_GINTSTS);
1625         s5pc1xx_otg_write_reg(int_status, OTG_GINTSTS);
1626
1627         if (int_status & INT_RESET) {
1628                 s5pc1xx_otg_write_reg(INT_RESET, OTG_GINTSTS);
1629                 s5p_usb_reset();
1630         }
1631
1632         if (int_status & INT_ENUMDONE) {
1633                 s5pc1xx_otg_write_reg(INT_ENUMDONE, OTG_GINTSTS);
1634
1635                 tmp = s5p_usb_set_init();
1636                 if (tmp == 0)
1637                         return;
1638         }
1639
1640         if (int_status & INT_RESUME) {
1641                 s5pc1xx_otg_write_reg(INT_RESUME, OTG_GINTSTS);
1642
1643                 if (SUSPEND_RESUME_ON) {
1644                         s5pc1xx_otg_write_reg(s5pc1xx_otg_read_reg(OTG_PCGCCTRL) &
1645                                         ~(1 << 0), OTG_PCGCCTRL);
1646                 }
1647         }
1648
1649         if (int_status & INT_SUSPEND) {
1650                 s5pc1xx_otg_write_reg(INT_SUSPEND, OTG_GINTSTS);
1651
1652                 if (SUSPEND_RESUME_ON) {
1653                         s5pc1xx_otg_write_reg(s5pc1xx_otg_read_reg(OTG_PCGCCTRL) |
1654                                         (1 << 0), OTG_PCGCCTRL);
1655                 }
1656         }
1657
1658         if (int_status & INT_RX_FIFO_NOT_EMPTY) {
1659                 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1660                                 INT_ENUMDONE | INT_RESET | INT_SUSPEND,
1661                                 OTG_GINTMSK);
1662
1663                 s5p_usb_pkt_receive();
1664
1665                 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1666                                 INT_ENUMDONE | INT_RESET | INT_SUSPEND |
1667                                 INT_RX_FIFO_NOT_EMPTY, OTG_GINTMSK);
1668         }
1669
1670         if ((int_status & INT_IN_EP) || (int_status & INT_OUT_EP))
1671                 s5p_usb_transfer();
1672 }