2 * Copyright (C) 2009 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/errno.h>
25 #include <asm/arch/power.h>
26 #include "usb-hs-otg.h"
33 int s5p_usb_connected;
35 USB_OPMODE op_mode = USB_CPU;
36 USB_SPEED speed = USB_HIGH;
38 USB_OPMODE op_mode = USB_DMA;
39 USB_SPEED speed = USB_FULL;
43 get_status_t get_status;
47 EP0, EP1, EP2, EP3, EP4
50 /*------------------------------------------------*/
54 EP0_STATE_GD_DEV_0 = 11,
55 EP0_STATE_GD_DEV_1 = 12,
56 EP0_STATE_GD_DEV_2 = 13,
57 EP0_STATE_GD_CFG_0 = 21,
58 EP0_STATE_GD_CFG_1 = 22,
59 EP0_STATE_GD_CFG_2 = 23,
60 EP0_STATE_GD_CFG_3 = 24,
61 EP0_STATE_GD_CFG_4 = 25,
62 EP0_STATE_GD_STR_I0 = 30,
63 EP0_STATE_GD_STR_I1 = 31,
64 EP0_STATE_GD_STR_I2 = 32,
65 EP0_STATE_GD_DEV_QUALIFIER = 33,
66 EP0_STATE_INTERFACE_GET = 34,
67 EP0_STATE_GET_STATUS0 = 35,
68 EP0_STATE_GET_STATUS1 = 36,
69 EP0_STATE_GET_STATUS2 = 37,
70 EP0_STATE_GET_STATUS3 = 38,
71 EP0_STATE_GET_STATUS4 = 39,
72 EP0_STATE_GD_OTHER_SPEED = 40,
73 EP0_STATE_GD_CFG_ONLY_0 = 41,
74 EP0_STATE_GD_CFG_ONLY_1 = 42,
75 EP0_STATE_GD_IF_ONLY_0 = 44,
76 EP0_STATE_GD_IF_ONLY_1 = 45,
77 EP0_STATE_GD_EP0_ONLY_0 = 46,
78 EP0_STATE_GD_EP1_ONLY_0 = 47,
79 EP0_STATE_GD_EP2_ONLY_0 = 48,
80 EP0_STATE_GD_EP3_ONLY_0 = 49,
81 EP0_STATE_GD_OTHER_SPEED_HIGH_1 = 51,
82 EP0_STATE_GD_OTHER_SPEED_HIGH_2 = 52,
83 EP0_STATE_GD_OTHER_SPEED_HIGH_3 = 53
86 /*definitions related to CSR setting */
89 #define B_SESSION_VALID (0x1 << 19)
90 #define A_SESSION_VALID (0x1 << 18)
93 #define PTXFE_HALF (0<<8)
94 #define PTXFE_ZERO (1<<8)
95 #define NPTXFE_HALF (0<<7)
96 #define NPTXFE_ZERO (1<<7)
97 #define MODE_SLAVE (0<<5)
98 #define MODE_DMA (1<<5)
99 #define BURST_SINGLE (0<<1)
100 #define BURST_INCR (1<<1)
101 #define BURST_INCR4 (3<<1)
102 #define BURST_INCR8 (5<<1)
103 #define BURST_INCR16 (7<<1)
104 #define GBL_INT_UNMASK (1<<0)
105 #define GBL_INT_MASK (0<<0)
108 #define AHB_MASTER_IDLE (1u<<31)
109 #define CORE_SOFT_RESET (0x1<<0)
111 /* OTG_GINTSTS/OTG_GINTMSK core interrupt register */
112 #define INT_RESUME (1u<<31)
113 #define INT_DISCONN (0x1<<29)
114 #define INT_CONN_ID_STS_CNG (0x1<<28)
115 #define INT_OUT_EP (0x1<<19)
116 #define INT_IN_EP (0x1<<18)
117 #define INT_ENUMDONE (0x1<<13)
118 #define INT_RESET (0x1<<12)
119 #define INT_SUSPEND (0x1<<11)
120 #define INT_TX_FIFO_EMPTY (0x1<<5)
121 #define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
122 #define INT_SOF (0x1<<3)
123 #define INT_DEV_MODE (0x0<<0)
124 #define INT_HOST_MODE (0x1<<1)
125 #define INT_OTG (0x1<<2)
127 /* OTG_GRXSTSP STATUS*/
128 #define GLOBAL_OUT_NAK (0x1<<17)
129 #define OUT_PKT_RECEIVED (0x2<<17)
130 #define OUT_TRNASFER_COMPLETED (0x3<<17)
131 #define SETUP_TRANSACTION_COMPLETED (0x4<<17)
132 #define SETUP_PKT_RECEIVED (0x6<<17)
134 /* OTG_DCTL device control register */
135 #define NORMAL_OPERATION (0x1<<0)
136 #define SOFT_DISCONNECT (0x1<<1)
137 #define TEST_J_MODE (TEST_J<<4)
138 #define TEST_K_MODE (TEST_K<<4)
139 #define TEST_SE0_NAK_MODE (TEST_SE0_NAK<<4)
140 #define TEST_PACKET_MODE (TEST_PACKET<<4)
141 #define TEST_FORCE_ENABLE_MODE (TEST_FORCE_ENABLE<<4)
142 #define TEST_CONTROL_FIELD (0x7<<4)
144 /* OTG_DAINT device all endpoint interrupt register */
145 #define INT_IN_EP0 (0x1<<0)
146 #define INT_IN_EP1 (0x1<<1)
147 #define INT_IN_EP3 (0x1<<3)
148 #define INT_OUT_EP0 (0x1<<16)
149 #define INT_OUT_EP2 (0x1<<18)
150 #define INT_OUT_EP4 (0x1<<20)
152 /* OTG_DIEPCTL0/OTG_DOEPCTL0 */
153 #define DEPCTL_EPENA (0x1<<31)
154 #define DEPCTL_EPDIS (0x1<<30)
155 #define DEPCTL_SNAK (0x1<<27)
156 #define DEPCTL_CNAK (0x1<<26)
157 #define DEPCTL_CTRL_TYPE (EP_TYPE_CONTROL<<18)
158 #define DEPCTL_ISO_TYPE (EP_TYPE_ISOCHRONOUS<<18)
159 #define DEPCTL_BULK_TYPE (EP_TYPE_BULK<<18)
160 #define DEPCTL_INTR_TYPE (EP_TYPE_INTERRUPT<<18)
161 #define DEPCTL_USBACTEP (0x1<<15)
163 /*ep0 enable, clear nak, next ep0, max 64byte */
164 #define EPEN_CNAK_EP0_64 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(0<<0))
166 /*ep0 enable, clear nak, next ep0, 8byte */
167 #define EPEN_CNAK_EP0_8 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(3<<0))
169 /* DIEPCTLn/DOEPCTLn */
170 #define BACK2BACK_SETUP_RECEIVED (0x1<<6)
171 #define INTKN_TXFEMP (0x1<<4)
172 #define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
173 #define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
174 #define AHB_ERROR (0x1<<2)
175 #define TRANSFER_DONE (0x1<<0)
177 /* codes representing languages */
178 const u8 string_desc0[] = {
179 4, STRING_DESCRIPTOR, LANGID_US_L, LANGID_US_H,
182 #ifdef CONFIG_SAMSUNG_USB
183 const u8 string_desc1[] = /* Manufacturer */
185 (0x14 + 2), STRING_DESCRIPTOR,
186 'S', 0x0, '/', 0x0, 'W', 0x0, ' ', 0x0, 'C', 0x0,
187 'e', 0x0, 'n', 0x0, 't', 0x0, 'e', 0x0, 'r', 0x0,
190 const u8 string_desc1[] = /* Manufacturer */
192 (0x14 + 2), STRING_DESCRIPTOR,
193 'S', 0x0, 'y', 0x0, 's', 0x0, 't', 0x0, 'e', 0x0,
194 'm', 0x0, ' ', 0x0, 'M', 0x0, 'C', 0x0, 'U', 0x0,
198 #ifdef CONFIG_SAMSUNG_USB
199 const u8 string_desc2[] = /* Product */
201 (0x22 + 2), STRING_DESCRIPTOR,
202 'S', 0x0, 'A', 0x0, 'M', 0x0, 'S', 0x0, 'U', 0x0,
203 'N', 0x0, 'G', 0x0, ' ', 0x0, 'X', 0x0, 'O', 0x0,
204 ' ', 0x0, 'D', 0x0, 'R', 0x0, 'I', 0x0, 'V', 0x0,
208 const u8 string_desc2[] = /* Product */
210 (0x2a + 2), STRING_DESCRIPTOR,
211 'S', 0x0, 'E', 0x0, 'C', 0x0, ' ', 0x0, 'S', 0x0,
212 '3', 0x0, 'C', 0x0, '6', 0x0, '4', 0x0, '0', 0x0,
213 '0', 0x0, 'X', 0x0, ' ', 0x0, 'T', 0x0, 'e', 0x0,
214 's', 0x0, 't', 0x0, ' ', 0x0, 'B', 0x0, '/', 0x0,
219 /* setting the device qualifier descriptor and a string descriptor */
220 const u8 qualifier_desc[] = {
221 0x0a, /* 0 desc size */
222 0x06, /* 1 desc type (DEVICE_QUALIFIER) */
223 0x00, /* 2 USB release */
224 0x02, /* 3 => 2.00 */
226 0x00, /* 5 subclass */
227 0x00, /* 6 protocol */
228 64, /* 7 max pack size */
229 0x01, /* 8 number of other-speed configuration */
230 0x00, /* 9 reserved */
233 const u8 config_full[] = {
234 0x09, /* 0 desc size */
235 0x07, /* 1 desc type (other speed) */
236 0x20, /* 2 Total length of data returned */
238 0x01, /* 4 Number of interfaces */
239 0x01, /* 5 value to use to select configuration */
240 0x00, /* 6 index of string desc */
241 /* 7 same as configuration desc */
242 CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED,
243 0x19, /* 8 same as configuration desc */
247 const u8 config_full_total[] = {
248 0x09, 0x07, 0x20, 0x00, 0x01, 0x01, 0x00, 0xC0, 0x19,
249 0x09, 0x04, 0x00, 0x00, 0x02, 0xff, 0x00, 0x00, 0x00,
250 0x07, 0x05, 0x83, 0x02, 0x40, 0x00, 0x00,
251 0x07, 0x05, 0x04, 0x02, 0x40, 0x00, 0x00
254 const u8 config_high[] = {
255 0x09, /* 0 desc size */
256 0x07, /* 1 desc type (other speed) */
257 0x20, /* 2 Total length of data returned */
259 0x01, /* 4 Number of interfaces */
260 0x01, /* 5 value to use to select configuration */
261 0x00, /* 6 index of string desc */
262 /* 7 same as configuration desc */
263 CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED,
264 0x19, /* 8 same as configuration desc */
268 const u8 config_high_total[] = {
269 0x09, 0x07, 0x20, 0x00, 0x01, 0x01, 0x00, 0xC0, 0x19,
270 0x09, 0x04, 0x00, 0x00, 0x02, 0xff, 0x00, 0x00, 0x00,
271 0x07, 0x05, 0x81, 0x02, 0x00, 0x02, 0x00,
272 0x07, 0x05, 0x02, 0x02, 0x00, 0x02, 0x00
275 /* Descriptor size */
276 enum DESCRIPTOR_SIZE {
277 DEVICE_DESC_SIZE = sizeof(device_desc_t),
278 STRING_DESC0_SIZE = sizeof(string_desc0),
279 STRING_DESC1_SIZE = sizeof(string_desc1),
280 STRING_DESC2_SIZE = sizeof(string_desc2),
281 CONFIG_DESC_SIZE = sizeof(config_desc_t),
282 INTERFACE_DESC_SIZE = sizeof(intf_desc_t),
283 ENDPOINT_DESC_SIZE = sizeof(ep_desc_t),
284 DEVICE_QUALIFIER_SIZE = sizeof(qualifier_desc),
285 OTHER_SPEED_CFG_SIZE = 9
288 /*32 <cfg desc>+<if desc>+<endp0 desc>+<endp1 desc>*/
289 #define CONFIG_DESC_TOTAL_SIZE \
290 (CONFIG_DESC_SIZE+INTERFACE_DESC_SIZE+ENDPOINT_DESC_SIZE*2)
292 static unsigned int phy_base;
293 static unsigned int otg_base;
295 static inline void s5p_usb_init_base(void)
297 if (cpu_is_s5pc110()) {
298 phy_base = S5PC110_PHY_BASE;
299 otg_base = S5PC110_OTG_BASE;
301 phy_base = S5PC100_PHY_BASE;
302 otg_base = S5PC100_OTG_BASE;
306 static inline int s5pc1xx_phy_read_reg(int offset)
308 return readl(phy_base + offset);
311 static inline void s5pc1xx_phy_write_reg(int value, int offset)
313 writel(value, phy_base + offset);
316 static inline int s5pc1xx_otg_read_reg(int offset)
318 return readl(otg_base + offset);
321 static inline void s5pc1xx_otg_write_reg(int value, int offset)
323 writel(value, otg_base + offset);
326 static void s5p_usb_init_phy(void)
328 if (cpu_is_s5pc110()) {
329 s5pc1xx_phy_write_reg(0xA0, OTG_PHYPWR);
330 s5pc1xx_phy_write_reg(0x3, OTG_PHYCTRL);
332 s5pc1xx_phy_write_reg(0x0, OTG_PHYPWR);
333 #ifdef CONFIG_OTG_CLK_OSCC
334 s5pc1xx_phy_write_reg(0x22, OTG_PHYCTRL);
336 s5pc1xx_phy_write_reg(0x2, OTG_PHYCTRL);
340 s5pc1xx_phy_write_reg(0x1, OTG_RSTCON);
342 s5pc1xx_phy_write_reg(0x0, OTG_RSTCON);
346 int s5p_usb_detect_irq(void)
349 status = s5pc1xx_otg_read_reg(OTG_GINTSTS);
350 return (status & 0x800c3810);
353 void s5p_usb_clear_irq(void)
355 s5pc1xx_otg_write_reg(0xffffffff, OTG_GINTSTS);
358 static void s5p_usb_core_soft_reset(void)
362 s5pc1xx_otg_write_reg(CORE_SOFT_RESET, OTG_GRSTCTL);
365 tmp = s5pc1xx_otg_read_reg(OTG_GRSTCTL);
366 } while (!(tmp & AHB_MASTER_IDLE));
369 static void s5p_usb_wait_cable_insert(void)
377 tmp = s5pc1xx_otg_read_reg(OTG_GOTGCTL);
379 if (tmp & (B_SESSION_VALID | A_SESSION_VALID)) {
381 } else if (ucFirst == 1) {
382 printf("Insert a OTG cable into the connector!\n");
388 static void s5p_usb_init_core(void)
390 s5pc1xx_otg_write_reg(PTXFE_HALF | NPTXFE_HALF | MODE_SLAVE |
391 BURST_SINGLE | GBL_INT_UNMASK, OTG_GAHBCFG);
393 s5pc1xx_otg_write_reg(
394 0x0 << 15 /* PHY Low Power Clock sel */
395 | 0x1 << 14 /* Non-Periodic TxFIFO Rewind Enable */
396 | 0x5 << 10 /* Turnaround time */
397 | 0x0 << 9 /* 0:HNP disable, 1:HNP enable */
398 | 0x0 << 8 /* 0:SRP disable, 1:SRP enable */
399 | 0x0 << 7 /* ULPI DDR sel */
400 | 0x0 << 6 /* 0: high speed utmi+, 1: full speed serial */
401 | 0x0 << 4 /* 0: utmi+, 1:ulpi */
402 | 0x1 << 3 /* phy i/f 0:8bit, 1:16bit */
403 | 0x7 << 0, /* HS/FS Timeout* */
407 static void s5p_usb_check_current_mode(u8 *pucMode)
411 tmp = s5pc1xx_otg_read_reg(OTG_GINTSTS);
412 *pucMode = tmp & 0x1;
415 static void s5p_usb_soft_disconnect(int set)
419 tmp = s5pc1xx_otg_read_reg(OTG_DCTL);
421 tmp |= SOFT_DISCONNECT;
423 tmp &= ~SOFT_DISCONNECT;
424 s5pc1xx_otg_write_reg(tmp, OTG_DCTL);
427 static void s5p_usb_init_device(void)
429 s5pc1xx_otg_write_reg(1 << 18 | otg.speed << 0, OTG_DCFG);
431 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
432 INT_ENUMDONE | INT_RESET | INT_SUSPEND |
433 INT_RX_FIFO_NOT_EMPTY, OTG_GINTMSK);
436 int s5p_usbctl_init(void)
443 if (cpu_is_s5pc110()) {
444 reg = readl(S5PC110_USB_PHY_CON);
445 reg |= (1 << 0); /* USB PHY0 enable */
446 writel(reg, S5PC110_USB_PHY_CON);
448 reg = readl(S5PC100_OTHERS);
449 reg |= (1 << 16); /* unmask usb signal */
450 writel(reg, S5PC100_OTHERS);
455 otg.ep0_state = EP0_STATE_INIT;
456 otg.ep0_substate = 0;
459 s5p_usb_core_soft_reset();
460 s5p_usb_wait_cable_insert();
462 s5p_usb_check_current_mode(&ucMode);
464 if (ucMode == INT_DEV_MODE) {
465 s5p_usb_soft_disconnect(1);
467 s5p_usb_soft_disconnect(0);
468 s5p_usb_init_device();
471 printf("Error : Current Mode is Host\n");
476 int s5p_usbc_activate(void)
481 void s5p_usb_stop(void)
485 static void s5p_usb_set_inep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize)
487 if (type == EP_TYPE_CONTROL) {
488 s5pc1xx_otg_write_reg((pktcnt << 19) | (xfersize << 0),
490 } else if (type == EP_TYPE_BULK) {
491 s5pc1xx_otg_write_reg((1 << 29) | (pktcnt << 19) |
492 (xfersize << 0), OTG_DIEPTSIZ_IN);
496 static void s5p_usb_set_outep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize)
498 if (type == EP_TYPE_CONTROL) {
499 s5pc1xx_otg_write_reg((1 << 29) | (pktcnt << 19) |
500 (xfersize << 0), OTG_DOEPTSIZ0);
501 } else if (type == EP_TYPE_BULK) {
502 s5pc1xx_otg_write_reg((pktcnt << 19) | (xfersize << 0),
507 /* works on both aligned and unaligned buffers */
508 static void s5p_usb_write_ep0_fifo(u8 *buf, int num)
513 for (i = 0; i < num; i += 4) {
514 Wr_Data = ((*(buf + 3)) << 24) |
515 ((*(buf + 2)) << 16) |
516 ((*(buf + 1)) << 8) |
518 s5pc1xx_otg_write_reg(Wr_Data, OTG_EP0_FIFO);
523 /* optimized fifo access routines, warning: only aligned buffers are supported */
524 static inline void s5p_usb_write_in_fifo(u8 *buf, int num)
526 u32 fifo = otg_base + OTG_IN_FIFO;
530 for (i = 0; i < num; i += 4)
534 static inline void s5p_usb_read_out_fifo(u8 *buf, int num)
536 u32 fifo = otg_base + OTG_OUT_FIFO;
540 for (i = 0; i < num; i += 4)
544 static void s5p_usb_get_desc(void)
546 switch (otg.dev_req.wValue_H) {
547 case DEVICE_DESCRIPTOR:
548 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
549 otg.dev_req.wLength_L);
550 otg.ep0_state = EP0_STATE_GD_DEV_0;
553 case CONFIGURATION_DESCRIPTOR:
554 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
555 otg.dev_req.wLength_L);
557 if (otg.req_length > CONFIG_DESC_SIZE)
558 otg.ep0_state = EP0_STATE_GD_CFG_0;
560 otg.ep0_state = EP0_STATE_GD_CFG_ONLY_0;
563 case STRING_DESCRIPTOR:
564 switch (otg.dev_req.wValue_L) {
566 otg.ep0_state = EP0_STATE_GD_STR_I0;
569 otg.ep0_state = EP0_STATE_GD_STR_I1;
572 otg.ep0_state = EP0_STATE_GD_STR_I2;
579 case ENDPOINT_DESCRIPTOR:
580 switch (otg.dev_req.wValue_L & 0xf) {
582 otg.ep0_state = EP0_STATE_GD_EP0_ONLY_0;
585 otg.ep0_state = EP0_STATE_GD_EP1_ONLY_0;
592 case DEVICE_QUALIFIER:
593 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
594 otg.dev_req.wLength_L);
595 otg.ep0_state = EP0_STATE_GD_DEV_QUALIFIER;
598 case OTHER_SPEED_CONFIGURATION:
599 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
600 otg.dev_req.wLength_L);
601 otg.ep0_state = EP0_STATE_GD_OTHER_SPEED;
606 static void s5p_usb_clear_feature(void)
608 switch (otg.dev_req.bmRequestType) {
609 case DEVICE_RECIPIENT:
610 if (otg.dev_req.wValue_L == 1)
614 case ENDPOINT_RECIPIENT:
615 if (otg.dev_req.wValue_L == 0) {
616 if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
617 get_status.ep_ctrl = 0;
620 if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
621 get_status.ep_in = 0;
624 if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
625 get_status.ep_out = 0;
632 otg.ep0_state = EP0_STATE_INIT;
635 static void s5p_usb_set_feature(void)
637 switch (otg.dev_req.bmRequestType) {
638 case DEVICE_RECIPIENT:
639 if (otg.dev_req.wValue_L == 1)
643 case ENDPOINT_RECIPIENT:
644 if (otg.dev_req.wValue_L == 0) {
645 if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
646 get_status.ep_ctrl = 1;
648 if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
649 get_status.ep_in = 1;
651 if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
652 get_status.ep_out = 1;
660 switch (otg.dev_req.wValue_L) {
662 /* TBD: additional processing if required */
672 otg.ep0_state = EP0_STATE_INIT;
675 static void s5p_usb_get_status(void)
677 switch (otg.dev_req.bmRequestType) {
678 case (0x80): /*device */
679 get_status.Device = ((u8) remode_wakeup << 1) | 0x1;
680 otg.ep0_state = EP0_STATE_GET_STATUS0;
683 case (0x81): /*interface */
684 get_status.Interface = 0;
685 otg.ep0_state = EP0_STATE_GET_STATUS1;
688 case (0x82): /*endpoint */
689 if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
690 otg.ep0_state = EP0_STATE_GET_STATUS2;
692 if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
693 otg.ep0_state = EP0_STATE_GET_STATUS3;
695 if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
696 otg.ep0_state = EP0_STATE_GET_STATUS4;
704 static void s5p_usb_ep0_int_hndlr(void)
707 u32 buf[2] = {0x0000, };
710 if (otg.ep0_state == EP0_STATE_INIT) {
711 for (i = 0; i < 2; i++)
712 buf[i] = s5pc1xx_otg_read_reg(OTG_EP0_FIFO);
714 otg.dev_req.bmRequestType = buf[0];
715 otg.dev_req.bRequest = buf[0] >> 8;
716 otg.dev_req.wValue_L = buf[0] >> 16;
717 otg.dev_req.wValue_H = buf[0] >> 24;
718 otg.dev_req.wIndex_L = buf[1];
719 otg.dev_req.wIndex_H = buf[1] >> 8;
720 otg.dev_req.wLength_L = buf[1] >> 16;
721 otg.dev_req.wLength_H = buf[1] >> 24;
723 switch (otg.dev_req.bRequest) {
724 case STANDARD_SET_ADDRESS:
725 /* Set Address Update bit */
726 addr = (otg.dev_req.wValue_L);
727 s5pc1xx_otg_write_reg(1 << 18 | addr << 4 | otg.speed << 0,
729 otg.ep0_state = EP0_STATE_INIT;
732 case STANDARD_SET_DESCRIPTOR:
735 case STANDARD_SET_CONFIGURATION:
736 /* Configuration value in configuration descriptor */
737 config_value = otg.dev_req.wValue_L;
739 otg.ep0_state = EP0_STATE_INIT;
741 s5p_usb_connected = 1;
744 case STANDARD_GET_CONFIGURATION:
745 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
747 /*ep0 enable, clear nak, next ep0, 8byte */
748 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
749 s5pc1xx_otg_write_reg(config_value, OTG_EP0_FIFO);
750 otg.ep0_state = EP0_STATE_INIT;
753 case STANDARD_GET_DESCRIPTOR:
757 case STANDARD_CLEAR_FEATURE:
758 s5p_usb_clear_feature();
761 case STANDARD_SET_FEATURE:
762 s5p_usb_set_feature();
765 case STANDARD_GET_STATUS:
766 s5p_usb_get_status();
769 case STANDARD_GET_INTERFACE:
770 otg.ep0_state = EP0_STATE_INTERFACE_GET;
773 case STANDARD_SET_INTERFACE:
774 get_intf.AlternateSetting = otg.dev_req.wValue_L;
775 otg.ep0_state = EP0_STATE_INIT;
778 case STANDARD_SYNCH_FRAME:
779 otg.ep0_state = EP0_STATE_INIT;
787 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.ctrl_max_pktsize);
789 /*clear nak, next ep0, 64byte */
790 s5pc1xx_otg_write_reg(((1 << 26) | (CONTROL_EP << 11) | (0 << 0)),
794 static void s5p_usb_set_otherspeed_conf_desc(u32 length)
796 /* Standard device descriptor */
798 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 9);
799 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
800 s5p_usb_write_ep0_fifo((u8 *) &config_full, 9);
801 } else if (length == 32) {
802 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 32);
803 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
804 s5p_usb_write_ep0_fifo((u8 *) &config_full_total, 32);
806 otg.ep0_state = EP0_STATE_INIT;
809 static void s5p_usb_transfer_ep0(void)
811 switch (otg.ep0_state) {
813 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 0);
815 /*ep0 enable, clear nak, next ep0, 8byte */
816 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
819 case EP0_STATE_GD_DEV_0:
820 /*ep0 enable, clear nak, next ep0, max 64byte */
821 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
822 if (otg.req_length < DEVICE_DESC_SIZE) {
823 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
825 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)),
828 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
830 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)),
833 otg.ep0_state = EP0_STATE_INIT;
836 case EP0_STATE_GD_DEV_1:
837 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
838 if (otg.req_length < (2 * FS_CTRL_PKT_SIZE)) {
839 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
841 otg.req_length - FS_CTRL_PKT_SIZE);
842 otg.ep0_state = EP0_STATE_INIT;
844 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
845 FS_CTRL_PKT_SIZE, FS_CTRL_PKT_SIZE);
846 otg.ep0_state = EP0_STATE_GD_DEV_2;
850 case EP0_STATE_GD_DEV_2:
851 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
852 if (otg.req_length < DEVICE_DESC_SIZE) {
853 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
854 (2 * FS_CTRL_PKT_SIZE),
855 otg.req_length - 2 * FS_CTRL_PKT_SIZE);
857 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
858 (2 * FS_CTRL_PKT_SIZE),
859 DEVICE_DESC_SIZE - 2 * FS_CTRL_PKT_SIZE);
861 otg.ep0_state = EP0_STATE_INIT;
864 case EP0_STATE_GD_CFG_0:
865 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
866 if (otg.req_length < CONFIG_DESC_TOTAL_SIZE) {
867 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
869 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
872 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
873 CONFIG_DESC_TOTAL_SIZE);
874 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
875 CONFIG_DESC_TOTAL_SIZE);
877 otg.ep0_state = EP0_STATE_INIT;
880 case EP0_STATE_GD_CFG_1:
881 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
882 if (otg.req_length < (2 * FS_CTRL_PKT_SIZE)) {
883 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
885 (otg.req_length - FS_CTRL_PKT_SIZE));
886 otg.ep0_state = EP0_STATE_INIT;
888 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
889 FS_CTRL_PKT_SIZE, FS_CTRL_PKT_SIZE);
890 otg.ep0_state = EP0_STATE_GD_CFG_2;
894 case EP0_STATE_GD_CFG_2:
895 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
896 if (otg.req_length < (3 * FS_CTRL_PKT_SIZE)) {
897 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
898 (2 * FS_CTRL_PKT_SIZE),
899 otg.req_length - 2 * FS_CTRL_PKT_SIZE);
900 otg.ep0_state = EP0_STATE_INIT;
902 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
903 (2 * FS_CTRL_PKT_SIZE), FS_CTRL_PKT_SIZE);
904 otg.ep0_state = EP0_STATE_GD_CFG_3;
908 case EP0_STATE_GD_CFG_3:
909 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
910 if (otg.req_length < (4 * FS_CTRL_PKT_SIZE)) {
911 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
912 (3 * FS_CTRL_PKT_SIZE),
913 otg.req_length - 3 * FS_CTRL_PKT_SIZE);
914 otg.ep0_state = EP0_STATE_INIT;
916 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
917 (3 * FS_CTRL_PKT_SIZE), FS_CTRL_PKT_SIZE);
918 otg.ep0_state = EP0_STATE_GD_CFG_4;
922 case EP0_STATE_GD_CFG_4:
923 otg.ep0_state = EP0_STATE_INIT;
926 case EP0_STATE_GD_DEV_QUALIFIER:
927 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
928 if (otg.req_length < 10) {
929 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
931 s5p_usb_write_ep0_fifo((u8 *)qualifier_desc,
934 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 10);
935 s5p_usb_write_ep0_fifo((u8 *)qualifier_desc, 10);
937 otg.ep0_state = EP0_STATE_INIT;
940 case EP0_STATE_GD_OTHER_SPEED:
941 s5p_usb_set_otherspeed_conf_desc(otg.req_length);
944 case EP0_STATE_GD_OTHER_SPEED_HIGH_1:
945 if (otg.req_length == 9) {
946 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
947 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
948 s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 8, 1);
949 otg.ep0_state = EP0_STATE_INIT;
951 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
952 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
953 s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 8, 8);
954 otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_2;
958 case EP0_STATE_GD_OTHER_SPEED_HIGH_2:
959 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
960 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
961 s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 16, 8);
962 otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_3;
965 case EP0_STATE_GD_OTHER_SPEED_HIGH_3:
966 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
967 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
968 s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 24, 8);
969 otg.ep0_state = EP0_STATE_INIT;
972 case EP0_STATE_GD_CFG_ONLY_0:
973 if (otg.req_length < CONFIG_DESC_SIZE) {
974 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
976 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
977 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
980 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
982 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
983 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
986 otg.ep0_state = EP0_STATE_INIT;
989 case EP0_STATE_GD_CFG_ONLY_1:
990 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
991 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
993 CONFIG_DESC_SIZE - FS_CTRL_PKT_SIZE);
994 otg.ep0_state = EP0_STATE_INIT;
997 case EP0_STATE_GD_IF_ONLY_0:
998 if (otg.req_length < INTERFACE_DESC_SIZE) {
999 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
1001 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1002 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.intf)),
1005 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
1006 INTERFACE_DESC_SIZE);
1007 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1008 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.intf)),
1009 INTERFACE_DESC_SIZE);
1011 otg.ep0_state = EP0_STATE_INIT;
1014 case EP0_STATE_GD_IF_ONLY_1:
1015 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1016 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.intf)) +
1018 INTERFACE_DESC_SIZE - FS_CTRL_PKT_SIZE);
1019 otg.ep0_state = EP0_STATE_INIT;
1022 case EP0_STATE_GD_EP0_ONLY_0:
1023 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1024 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, ENDPOINT_DESC_SIZE);
1025 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.ep1)),
1026 ENDPOINT_DESC_SIZE);
1027 otg.ep0_state = EP0_STATE_INIT;
1030 case EP0_STATE_GD_EP1_ONLY_0:
1031 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, ENDPOINT_DESC_SIZE);
1032 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1033 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.ep2)),
1034 ENDPOINT_DESC_SIZE);
1035 otg.ep0_state = EP0_STATE_INIT;
1038 case EP0_STATE_GD_STR_I0:
1039 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, STRING_DESC0_SIZE);
1040 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1041 s5p_usb_write_ep0_fifo((u8 *)string_desc0, STRING_DESC0_SIZE);
1042 otg.ep0_state = EP0_STATE_INIT;
1045 case EP0_STATE_GD_STR_I1:
1046 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, sizeof(string_desc1));
1047 if ((otg.ep0_substate * otg.ctrl_max_pktsize +
1048 otg.ctrl_max_pktsize) < sizeof(string_desc1)) {
1049 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1051 s5p_usb_write_ep0_fifo((u8 *)string_desc1 +
1052 (otg.ep0_substate * otg.ctrl_max_pktsize),
1053 otg.ctrl_max_pktsize);
1054 otg.ep0_state = EP0_STATE_GD_STR_I1;
1057 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1059 s5p_usb_write_ep0_fifo((u8 *)string_desc1 +
1060 (otg.ep0_substate * otg.ctrl_max_pktsize),
1061 sizeof(string_desc1) - (otg.ep0_substate *
1062 otg.ctrl_max_pktsize));
1063 otg.ep0_state = EP0_STATE_INIT;
1064 otg.ep0_substate = 0;
1068 case EP0_STATE_GD_STR_I2:
1069 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, sizeof(string_desc2));
1070 if ((otg.ep0_substate * otg.ctrl_max_pktsize +
1071 otg.ctrl_max_pktsize) < sizeof(string_desc2)) {
1072 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1074 s5p_usb_write_ep0_fifo((u8 *) string_desc2 +
1075 (otg.ep0_substate * otg.ctrl_max_pktsize),
1076 otg.ctrl_max_pktsize);
1077 otg.ep0_state = EP0_STATE_GD_STR_I2;
1080 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1081 s5p_usb_write_ep0_fifo((u8 *) string_desc2 +
1082 (otg.ep0_substate * otg.ctrl_max_pktsize),
1083 sizeof(string_desc2) - (otg.ep0_substate *
1084 otg.ctrl_max_pktsize));
1085 otg.ep0_state = EP0_STATE_INIT;
1086 otg.ep0_substate = 0;
1090 case EP0_STATE_INTERFACE_GET:
1091 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1092 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1093 s5p_usb_write_ep0_fifo((u8 *) &get_intf, 1);
1094 otg.ep0_state = EP0_STATE_INIT;
1097 case EP0_STATE_GET_STATUS0:
1098 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1099 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1100 s5p_usb_write_ep0_fifo((u8 *) &get_status, 1);
1101 otg.ep0_state = EP0_STATE_INIT;
1104 case EP0_STATE_GET_STATUS1:
1105 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1106 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1107 s5p_usb_write_ep0_fifo((u8 *) &get_status + 1, 1);
1108 otg.ep0_state = EP0_STATE_INIT;
1111 case EP0_STATE_GET_STATUS2:
1112 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1113 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1114 s5p_usb_write_ep0_fifo((u8 *) &get_status + 2, 1);
1115 otg.ep0_state = EP0_STATE_INIT;
1118 case EP0_STATE_GET_STATUS3:
1119 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1120 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1121 s5p_usb_write_ep0_fifo((u8 *) &get_status + 3, 1);
1122 otg.ep0_state = EP0_STATE_INIT;
1125 case EP0_STATE_GET_STATUS4:
1126 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1127 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1128 s5p_usb_write_ep0_fifo((u8 *) &get_status + 4, 1);
1129 otg.ep0_state = EP0_STATE_INIT;
1137 void s5p_usb_tx(char *tx_data, int tx_size)
1139 otg.up_ptr = (u8 *) tx_data;
1140 otg.up_addr = (u32) tx_data;
1141 otg.up_size = tx_size;
1143 if (otg.op_mode == USB_CPU) {
1144 if (otg.up_size > otg.bulkin_max_pktsize) {
1145 s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1,
1146 otg.bulkin_max_pktsize);
1148 s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1, otg.up_size);
1151 /*ep1 enable, clear nak, bulk, usb active, max pkt */
1152 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1153 otg.bulkin_max_pktsize << 0, OTG_DIEPCTL_IN);
1155 s5p_usb_write_in_fifo(otg.up_ptr, otg.up_size);
1156 } else if ((otg.op_mode == USB_DMA) && (otg.up_size > 0)) {
1157 u32 pktcnt, remainder;
1159 s5pc1xx_otg_write_reg(MODE_DMA | BURST_INCR4 | GBL_INT_UNMASK,
1161 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1162 INT_ENUMDONE | INT_RESET | INT_SUSPEND,
1165 s5pc1xx_otg_write_reg((u32) otg.up_ptr, OTG_DIEPDMA_IN);
1167 pktcnt = (u32) (otg.up_size / otg.bulkin_max_pktsize);
1168 remainder = (u32) (otg.up_size % otg.bulkin_max_pktsize);
1172 if (pktcnt > 1023) {
1173 s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1023,
1174 otg.bulkin_max_pktsize * 1023);
1176 s5p_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt,
1180 /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */
1181 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1182 BULK_IN_EP << 11 | otg.bulkin_max_pktsize << 0,
1187 static void s5p_usb_rx(u32 fifo_cnt_byte)
1189 if (otg.op_mode == USB_CPU) {
1190 s5p_usb_read_out_fifo((u8 *)otg.dn_ptr, fifo_cnt_byte);
1191 otg.dn_ptr += fifo_cnt_byte;
1193 s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1,
1194 otg.bulkout_max_pktsize);
1196 /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt */
1197 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1198 otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1200 if (((u32)otg.dn_ptr - otg.dn_addr) >= (otg.dn_filesize))
1201 s5p_receive_done = 1;
1202 } else if (otg.dn_filesize > otg.bulkout_max_pktsize) {
1203 u32 pkt_cnt, remain_cnt;
1205 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1206 INT_ENUMDONE | INT_RESET | INT_SUSPEND,
1208 s5pc1xx_otg_write_reg(MODE_DMA | BURST_INCR4 | GBL_INT_UNMASK,
1210 s5pc1xx_otg_write_reg((u32) otg.dn_ptr, OTG_DOEPDMA_OUT);
1211 pkt_cnt = (u32)(otg.dn_filesize - otg.bulkout_max_pktsize) /
1212 otg.bulkout_max_pktsize;
1213 remain_cnt = (u32)((otg.dn_filesize - otg.bulkout_max_pktsize) %
1214 otg.bulkout_max_pktsize);
1216 if (remain_cnt != 0)
1219 if (pkt_cnt > 1023) {
1220 s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1023,
1221 otg.bulkout_max_pktsize * 1023);
1223 s5p_usb_set_outep_xfersize(EP_TYPE_BULK, pkt_cnt,
1224 otg.dn_filesize - otg.bulkout_max_pktsize);
1227 /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt */
1228 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1229 otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1233 static void s5p_usb_int_bulkout(u32 fifo_cnt_byte)
1235 s5p_usb_rx(fifo_cnt_byte);
1238 static void s5p_usb_dma_in_done(void)
1242 otg.up_ptr = (u8 *)s5pc1xx_otg_read_reg(OTG_DIEPDMA_IN);
1243 remain_cnt = otg.up_size - ((u32) otg.up_ptr - otg.up_addr);
1245 if (remain_cnt > 0) {
1246 u32 pktcnt, remainder;
1247 pktcnt = (u32)(remain_cnt / otg.bulkin_max_pktsize);
1248 remainder = (u32)(remain_cnt % otg.bulkin_max_pktsize);
1253 if (pktcnt > 1023) {
1254 s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1023,
1255 otg.bulkin_max_pktsize * 1023);
1257 s5p_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt,
1261 /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */
1262 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1263 BULK_IN_EP << 11 | otg.bulkin_max_pktsize << 0,
1266 s5p_receive_done = 1;
1270 static void s5p_usb_dma_out_done(void)
1274 otg.dn_ptr = (u8 *)s5pc1xx_otg_read_reg(OTG_DOEPDMA_OUT);
1276 remain_cnt = otg.dn_filesize - ((u32) otg.dn_ptr - otg.dn_addr + 8);
1278 if (remain_cnt > 0) {
1279 u32 pktcnt, remainder;
1280 pktcnt = (u32)(remain_cnt / otg.bulkout_max_pktsize);
1281 remainder = (u32)(remain_cnt % otg.bulkout_max_pktsize);
1286 if (pktcnt > 1023) {
1287 s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1023,
1288 otg.bulkout_max_pktsize * 1023);
1290 s5p_usb_set_outep_xfersize(EP_TYPE_BULK, pktcnt,
1294 /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64 */
1295 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1296 otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1298 udelay(500); /*for FPGA ??? */
1302 static void s5p_usb_set_all_outep_nak(void)
1307 for (i = 0; i < 16; i++) {
1308 tmp = s5pc1xx_otg_read_reg(OTG_DOEPCTL0 + 0x20 * i);
1310 s5pc1xx_otg_write_reg(tmp, OTG_DOEPCTL0 + 0x20 * i);
1314 static void s5p_usb_clear_all_outep_nak(void)
1319 for (i = 0; i < 16; i++) {
1320 tmp = s5pc1xx_otg_read_reg(OTG_DOEPCTL0 + 0x20 * i);
1321 tmp |= (DEPCTL_EPENA | DEPCTL_CNAK);
1322 s5pc1xx_otg_write_reg(tmp, OTG_DOEPCTL0 + 0x20 * i);
1326 static void s5p_usb_set_max_pktsize(USB_SPEED speed)
1328 otg.speed = USB_HIGH;
1329 otg.ctrl_max_pktsize = HS_CTRL_PKT_SIZE;
1330 otg.bulkin_max_pktsize = HS_BULK_PKT_SIZE;
1331 otg.bulkout_max_pktsize = HS_BULK_PKT_SIZE;
1334 static void s5p_usb_set_endpoint(void)
1336 /* Unmask OTG_DAINT source */
1337 s5pc1xx_otg_write_reg(0xff, OTG_DIEPINT0);
1338 s5pc1xx_otg_write_reg(0xff, OTG_DOEPINT0);
1339 s5pc1xx_otg_write_reg(0xff, OTG_DIEPINT_IN);
1340 s5pc1xx_otg_write_reg(0xff, OTG_DOEPINT_OUT);
1344 s5pc1xx_otg_write_reg(((1 << 26) | (CONTROL_EP << 11) | (0 << 0)),
1346 /*ep0 enable, clear nak */
1347 s5pc1xx_otg_write_reg((1u << 31) | (1 << 26) | (0 << 0),
1351 static void s5p_usb_set_descriptors(void)
1353 #if defined (CONFIG_SAMSUNG_USB)
1354 otg.desc.dev.bLength = DEVICE_DESC_SIZE;
1355 otg.desc.dev.bDescriptorType = DEVICE_DESCRIPTOR;
1356 otg.desc.dev.bDeviceClass = 0xFF;
1357 otg.desc.dev.bDeviceSubClass = 0x0;
1358 otg.desc.dev.bDeviceProtocol = 0x0;
1359 otg.desc.dev.bMaxPacketSize0 = otg.ctrl_max_pktsize;
1360 otg.desc.dev.idVendorL = 0xE8;
1361 otg.desc.dev.idVendorH = 0x04;
1362 otg.desc.dev.idProductL = 0x04;
1363 otg.desc.dev.idProductH = 0x12;
1364 otg.desc.dev.iManufacturer = 0x0;
1365 otg.desc.dev.iProduct = 0x2;
1366 otg.desc.dev.iSerialNumber = 0x0;
1367 otg.desc.dev.bNumConfigurations = 0x1;
1368 otg.desc.dev.bcdUSBL = 0x00;
1369 otg.desc.dev.bcdUSBH = 0x02;
1371 otg.desc.config.bLength = CONFIG_DESC_SIZE;
1372 otg.desc.config.bDescriptorType = CONFIGURATION_DESCRIPTOR;
1373 otg.desc.config.wTotalLengthL = CONFIG_DESC_TOTAL_SIZE;
1374 otg.desc.config.wTotalLengthH = 0;
1375 otg.desc.config.bNumInterfaces = 1;
1376 otg.desc.config.bConfigurationValue = 1;
1377 otg.desc.config.iConfiguration = 0;
1378 otg.desc.config.bmAttributes = CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED;
1379 otg.desc.config.maxPower = 50;
1381 otg.desc.dev.bLength = DEVICE_DESC_SIZE;
1382 otg.desc.dev.bDescriptorType = DEVICE_DESCRIPTOR;
1383 otg.desc.dev.bDeviceClass = 0xFF;
1384 otg.desc.dev.bDeviceSubClass = 0x0;
1385 otg.desc.dev.bDeviceProtocol = 0x0;
1386 otg.desc.dev.bMaxPacketSize0 = otg.ctrl_max_pktsize;
1387 otg.desc.dev.idVendorL = 0xE8;
1388 otg.desc.dev.idVendorH = 0x04;
1389 otg.desc.dev.idProductL = 0x34;
1390 otg.desc.dev.idProductH = 0x12;
1391 otg.desc.dev.bcdDeviceL = 0x00;
1392 otg.desc.dev.bcdDeviceH = 0x01;
1393 otg.desc.dev.iManufacturer = 0x1;
1394 otg.desc.dev.iProduct = 0x2;
1395 otg.desc.dev.iSerialNumber = 0x0;
1396 otg.desc.dev.bNumConfigurations = 0x1;
1397 otg.desc.dev.bcdUSBL = 0x00;
1398 otg.desc.dev.bcdUSBH = 0x02;
1400 otg.desc.config.bLength = CONFIG_DESC_SIZE;
1401 otg.desc.config.bDescriptorType = CONFIGURATION_DESCRIPTOR;
1402 otg.desc.config.wTotalLengthL = CONFIG_DESC_TOTAL_SIZE;
1403 otg.desc.config.wTotalLengthH = 0;
1404 otg.desc.config.bNumInterfaces = 1;
1405 otg.desc.config.bConfigurationValue = 1;
1406 otg.desc.config.iConfiguration = 0;
1407 otg.desc.config.bmAttributes = CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED;
1408 otg.desc.config.maxPower = 25;
1410 otg.desc.intf.bLength = INTERFACE_DESC_SIZE;
1411 otg.desc.intf.bDescriptorType = INTERFACE_DESCRIPTOR;
1412 otg.desc.intf.bInterfaceNumber = 0x0;
1413 otg.desc.intf.bAlternateSetting = 0x0;
1414 otg.desc.intf.bNumEndpoints = 2;
1415 otg.desc.intf.bInterfaceClass = 0xff;
1416 otg.desc.intf.bInterfaceSubClass = 0xff;
1417 otg.desc.intf.bInterfaceProtocol = 0xff;
1418 otg.desc.intf.iInterface = 0x0;
1420 otg.desc.ep1.bLength = ENDPOINT_DESC_SIZE;
1421 otg.desc.ep1.bDescriptorType = ENDPOINT_DESCRIPTOR;
1422 otg.desc.ep1.bEndpointAddress = BULK_IN_EP | EP_ADDR_IN;
1423 otg.desc.ep1.bmAttributes = EP_ATTR_BULK;
1424 otg.desc.ep1.wMaxPacketSizeL = (u8)otg.bulkin_max_pktsize;
1425 otg.desc.ep1.wMaxPacketSizeH = (u8)(otg.bulkin_max_pktsize >> 8);
1426 otg.desc.ep1.bInterval = 0x0;
1428 otg.desc.ep2.bLength = ENDPOINT_DESC_SIZE;
1429 otg.desc.ep2.bDescriptorType = ENDPOINT_DESCRIPTOR;
1430 otg.desc.ep2.bEndpointAddress = BULK_OUT_EP | EP_ADDR_OUT;
1431 otg.desc.ep2.bmAttributes = EP_ATTR_BULK;
1432 otg.desc.ep2.wMaxPacketSizeL = (u8)otg.bulkout_max_pktsize;
1433 otg.desc.ep2.wMaxPacketSizeH = (u8)(otg.bulkout_max_pktsize >> 8);
1434 otg.desc.ep2.bInterval = 0x0;
1437 static void s5p_usb_set_opmode(USB_OPMODE mode)
1441 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP | INT_ENUMDONE |
1442 INT_RESET | INT_SUSPEND | INT_RX_FIFO_NOT_EMPTY,
1445 s5pc1xx_otg_write_reg(MODE_SLAVE | BURST_SINGLE | GBL_INT_UNMASK,
1448 s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1, otg.bulkout_max_pktsize);
1449 s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1, 0);
1451 /*bulk out ep enable, clear nak, bulk, usb active, next ep3, max pkt */
1452 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1453 otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1455 /*bulk in ep enable, clear nak, bulk, usb active, next ep1, max pkt */
1456 s5pc1xx_otg_write_reg(0u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1457 otg.bulkin_max_pktsize << 0, OTG_DIEPCTL_IN);
1460 static void s5p_usb_reset(void)
1462 s5p_usb_set_all_outep_nak();
1464 otg.ep0_state = EP0_STATE_INIT;
1465 s5pc1xx_otg_write_reg(((1 << BULK_OUT_EP) | (1 << CONTROL_EP)) << 16 |
1466 ((1 << BULK_IN_EP) | (1 << CONTROL_EP)), OTG_DAINTMSK);
1467 s5pc1xx_otg_write_reg(CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR |
1468 TRANSFER_DONE, OTG_DOEPMSK);
1469 s5pc1xx_otg_write_reg(INTKN_TXFEMP | NON_ISO_IN_EP_TIMEOUT | AHB_ERROR |
1470 TRANSFER_DONE, OTG_DIEPMSK);
1473 s5pc1xx_otg_write_reg(RX_FIFO_SIZE, OTG_GRXFSIZ);
1475 /* Non Periodic Tx FIFO Size */
1476 s5pc1xx_otg_write_reg(NPTX_FIFO_SIZE << 16 | NPTX_FIFO_START_ADDR << 0,
1479 s5p_usb_clear_all_outep_nak();
1481 /*clear device address */
1482 s5pc1xx_otg_write_reg(s5pc1xx_otg_read_reg(OTG_DCFG) & ~(0x7f << 4),
1486 static int s5p_usb_set_init(void)
1490 status = s5pc1xx_otg_read_reg(OTG_DSTS);
1492 /* Set if Device is High speed or Full speed */
1493 if (((status & 0x6) >> 1) == USB_HIGH) {
1494 s5p_usb_set_max_pktsize(USB_HIGH);
1495 } else if (((status & 0x6) >> 1) == USB_FULL) {
1496 printf("Error: Don't support Full_Speed\n");
1499 printf("Error: Neither High_Speed nor Full_Speed\n");
1503 s5p_usb_set_endpoint();
1504 s5p_usb_set_descriptors();
1505 s5p_usb_set_opmode(op_mode);
1510 static void s5p_usb_pkt_receive(void)
1515 rx_status = s5pc1xx_otg_read_reg(OTG_GRXSTSP);
1517 if ((rx_status & (0xf << 17)) == SETUP_PKT_RECEIVED) {
1518 s5p_usb_ep0_int_hndlr();
1519 } else if ((rx_status & (0xf << 17)) == OUT_PKT_RECEIVED) {
1520 fifo_cnt_byte = (rx_status & 0x7ff0) >> 4;
1522 if ((rx_status & BULK_OUT_EP) && (fifo_cnt_byte)) {
1523 s5p_usb_int_bulkout(fifo_cnt_byte);
1524 if (otg.op_mode == USB_CPU) {
1525 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP |
1526 INT_IN_EP | INT_ENUMDONE | INT_RESET |
1527 INT_SUSPEND | INT_RX_FIFO_NOT_EMPTY,
1533 } else if ((rx_status & (0xf << 17)) == GLOBAL_OUT_NAK) {
1535 } else if ((rx_status & (0xf << 17)) == OUT_TRNASFER_COMPLETED) {
1537 } else if ((rx_status & (0xf << 17)) == SETUP_TRANSACTION_COMPLETED) {
1544 static void s5p_usb_transfer(void)
1550 ep_int = s5pc1xx_otg_read_reg(OTG_DAINT);
1552 if (ep_int & (1 << CONTROL_EP)) {
1553 ep_int_status = s5pc1xx_otg_read_reg(OTG_DIEPINT0);
1555 if (ep_int_status & INTKN_TXFEMP) {
1558 uNTxFifoSpace = s5pc1xx_otg_read_reg(OTG_GNPTXSTS)
1560 } while (uNTxFifoSpace < otg.ctrl_max_pktsize);
1562 s5p_usb_transfer_ep0();
1565 s5pc1xx_otg_write_reg(ep_int_status, OTG_DIEPINT0);
1568 if (ep_int & ((1 << CONTROL_EP) << 16)) {
1569 ep_int_status = s5pc1xx_otg_read_reg(OTG_DOEPINT0);
1571 s5p_usb_set_outep_xfersize(EP_TYPE_CONTROL, 1, 8);
1572 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26, OTG_DOEPCTL0);
1574 s5pc1xx_otg_write_reg(ep_int_status, OTG_DOEPINT0);
1577 if (ep_int & (1 << BULK_IN_EP)) {
1578 ep_int_status = s5pc1xx_otg_read_reg(OTG_DIEPINT_IN);
1580 s5pc1xx_otg_write_reg(ep_int_status, OTG_DIEPINT_IN);
1581 check_dma = s5pc1xx_otg_read_reg(OTG_GAHBCFG);
1583 if ((check_dma & MODE_DMA) && (ep_int_status & TRANSFER_DONE))
1584 s5p_usb_dma_in_done();
1587 if (ep_int & ((1 << BULK_OUT_EP) << 16)) {
1588 ep_int_status = s5pc1xx_otg_read_reg(OTG_DOEPINT_OUT);
1590 s5pc1xx_otg_write_reg(ep_int_status, OTG_DOEPINT_OUT);
1591 check_dma = s5pc1xx_otg_read_reg(OTG_GAHBCFG);
1593 if ((check_dma & MODE_DMA) && (ep_int_status & TRANSFER_DONE))
1594 s5p_usb_dma_out_done();
1598 void s5p_udc_int_hndlr(void)
1603 int_status = s5pc1xx_otg_read_reg(OTG_GINTSTS);
1604 s5pc1xx_otg_write_reg(int_status, OTG_GINTSTS);
1606 if (int_status & INT_RESET) {
1607 s5pc1xx_otg_write_reg(INT_RESET, OTG_GINTSTS);
1611 if (int_status & INT_ENUMDONE) {
1612 s5pc1xx_otg_write_reg(INT_ENUMDONE, OTG_GINTSTS);
1614 tmp = s5p_usb_set_init();
1619 if (int_status & INT_RESUME)
1620 s5pc1xx_otg_write_reg(INT_RESUME, OTG_GINTSTS);
1622 if (int_status & INT_SUSPEND)
1623 s5pc1xx_otg_write_reg(INT_SUSPEND, OTG_GINTSTS);
1625 if (int_status & INT_RX_FIFO_NOT_EMPTY) {
1626 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1627 INT_ENUMDONE | INT_RESET | INT_SUSPEND,
1630 s5p_usb_pkt_receive();
1632 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1633 INT_ENUMDONE | INT_RESET | INT_SUSPEND |
1634 INT_RX_FIFO_NOT_EMPTY, OTG_GINTMSK);
1637 if ((int_status & INT_IN_EP) || (int_status & INT_OUT_EP))