cpu/arm_cortexa8/s5pc1xx/usb-hs-otg.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22
  23 #include <command.h>
  24 #include <asm/errno.h>
  25 #include <asm/arch/power.h>
  26 #include "usb-hs-otg.h"
  27
  28 u32 remode_wakeup;
  29 u16 config_value;
  30
  31 int s5p_receive_done;
  32 int s5p_got_header;
  33 int s5p_usb_connected;
  34
  35 USB_OPMODE op_mode = USB_CPU;
  36 USB_SPEED speed = USB_HIGH;
  37 /*
  38 USB_OPMODE op_mode = USB_DMA;
  39 USB_SPEED speed = USB_FULL;
  40 */
  41
  42 otg_dev_t otg;
  43 get_status_t get_status;
  44 get_intf_t get_intf;
  45
  46 enum EP_INDEX {
  47         EP0, EP1, EP2, EP3, EP4
  48 };
  49
  50 /*------------------------------------------------*/
  51 /* EP0 state */
  52 enum EP0_STATE {
  53         EP0_STATE_INIT = 0,
  54         EP0_STATE_GD_DEV_0 = 11,
  55         EP0_STATE_GD_DEV_1 = 12,
  56         EP0_STATE_GD_DEV_2 = 13,
  57         EP0_STATE_GD_CFG_0 = 21,
  58         EP0_STATE_GD_CFG_1 = 22,
  59         EP0_STATE_GD_CFG_2 = 23,
  60         EP0_STATE_GD_CFG_3 = 24,
  61         EP0_STATE_GD_CFG_4 = 25,
  62         EP0_STATE_GD_STR_I0 = 30,
  63         EP0_STATE_GD_STR_I1 = 31,
  64         EP0_STATE_GD_STR_I2 = 32,
  65         EP0_STATE_GD_DEV_QUALIFIER = 33,
  66         EP0_STATE_INTERFACE_GET = 34,
  67         EP0_STATE_GET_STATUS0 = 35,
  68         EP0_STATE_GET_STATUS1 = 36,
  69         EP0_STATE_GET_STATUS2 = 37,
  70         EP0_STATE_GET_STATUS3 = 38,
  71         EP0_STATE_GET_STATUS4 = 39,
  72         EP0_STATE_GD_OTHER_SPEED = 40,
  73         EP0_STATE_GD_CFG_ONLY_0 = 41,
  74         EP0_STATE_GD_CFG_ONLY_1 = 42,
  75         EP0_STATE_GD_IF_ONLY_0 = 44,
  76         EP0_STATE_GD_IF_ONLY_1 = 45,
  77         EP0_STATE_GD_EP0_ONLY_0 = 46,
  78         EP0_STATE_GD_EP1_ONLY_0 = 47,
  79         EP0_STATE_GD_EP2_ONLY_0 = 48,
  80         EP0_STATE_GD_EP3_ONLY_0 = 49,
  81         EP0_STATE_GD_OTHER_SPEED_HIGH_1 = 51,
  82         EP0_STATE_GD_OTHER_SPEED_HIGH_2 = 52,
  83         EP0_STATE_GD_OTHER_SPEED_HIGH_3 = 53
  84 };
  85
  86 /*definitions related to CSR setting */
  87
  88 /* OTG_GOTGCTL*/
  89 #define B_SESSION_VALID         (0x1 << 19)
  90 #define A_SESSION_VALID         (0x1 << 18)
  91
  92 /* OTG_GAHBCFG*/
  93 #define PTXFE_HALF              (0<<8)
  94 #define PTXFE_ZERO              (1<<8)
  95 #define NPTXFE_HALF             (0<<7)
  96 #define NPTXFE_ZERO             (1<<7)
  97 #define MODE_SLAVE              (0<<5)
  98 #define MODE_DMA                (1<<5)
  99 #define BURST_SINGLE            (0<<1)
 100 #define BURST_INCR              (1<<1)
 101 #define BURST_INCR4             (3<<1)
 102 #define BURST_INCR8             (5<<1)
 103 #define BURST_INCR16            (7<<1)
 104 #define GBL_INT_UNMASK          (1<<0)
 105 #define GBL_INT_MASK            (0<<0)
 106
 107 /* OTG_GRSTCTL*/
 108 #define AHB_MASTER_IDLE         (1u<<31)
 109 #define CORE_SOFT_RESET         (0x1<<0)
 110
 111 /* OTG_GINTSTS/OTG_GINTMSK core interrupt register */
 112 #define INT_RESUME              (1u<<31)
 113 #define INT_DISCONN             (0x1<<29)
 114 #define INT_CONN_ID_STS_CNG     (0x1<<28)
 115 #define INT_OUT_EP              (0x1<<19)
 116 #define INT_IN_EP               (0x1<<18)
 117 #define INT_ENUMDONE            (0x1<<13)
 118 #define INT_RESET               (0x1<<12)
 119 #define INT_SUSPEND             (0x1<<11)
 120 #define INT_TX_FIFO_EMPTY       (0x1<<5)
 121 #define INT_RX_FIFO_NOT_EMPTY   (0x1<<4)
 122 #define INT_SOF                 (0x1<<3)
 123 #define INT_DEV_MODE            (0x0<<0)
 124 #define INT_HOST_MODE           (0x1<<1)
 125 #define INT_OTG                 (0x1<<2)
 126
 127 /* OTG_GRXSTSP STATUS*/
 128 #define GLOBAL_OUT_NAK                  (0x1<<17)
 129 #define OUT_PKT_RECEIVED                (0x2<<17)
 130 #define OUT_TRNASFER_COMPLETED          (0x3<<17)
 131 #define SETUP_TRANSACTION_COMPLETED     (0x4<<17)
 132 #define SETUP_PKT_RECEIVED              (0x6<<17)
 133
 134 /* OTG_DCTL device control register */
 135 #define NORMAL_OPERATION                (0x1<<0)
 136 #define SOFT_DISCONNECT                 (0x1<<1)
 137 #define TEST_J_MODE                     (TEST_J<<4)
 138 #define TEST_K_MODE                     (TEST_K<<4)
 139 #define TEST_SE0_NAK_MODE               (TEST_SE0_NAK<<4)
 140 #define TEST_PACKET_MODE                (TEST_PACKET<<4)
 141 #define TEST_FORCE_ENABLE_MODE          (TEST_FORCE_ENABLE<<4)
 142 #define TEST_CONTROL_FIELD              (0x7<<4)
 143
 144 /* OTG_DAINT device all endpoint interrupt register */
 145 #define INT_IN_EP0                      (0x1<<0)
 146 #define INT_IN_EP1                      (0x1<<1)
 147 #define INT_IN_EP3                      (0x1<<3)
 148 #define INT_OUT_EP0                     (0x1<<16)
 149 #define INT_OUT_EP2                     (0x1<<18)
 150 #define INT_OUT_EP4                     (0x1<<20)
 151
 152 /* OTG_DIEPCTL0/OTG_DOEPCTL0 */
 153 #define DEPCTL_EPENA                    (0x1<<31)
 154 #define DEPCTL_EPDIS                    (0x1<<30)
 155 #define DEPCTL_SNAK                     (0x1<<27)
 156 #define DEPCTL_CNAK                     (0x1<<26)
 157 #define DEPCTL_CTRL_TYPE                (EP_TYPE_CONTROL<<18)
 158 #define DEPCTL_ISO_TYPE                 (EP_TYPE_ISOCHRONOUS<<18)
 159 #define DEPCTL_BULK_TYPE                (EP_TYPE_BULK<<18)
 160 #define DEPCTL_INTR_TYPE                (EP_TYPE_INTERRUPT<<18)
 161 #define DEPCTL_USBACTEP                 (0x1<<15)
 162
 163 /*ep0 enable, clear nak, next ep0, max 64byte */
 164 #define EPEN_CNAK_EP0_64 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(0<<0))
 165
 166 /*ep0 enable, clear nak, next ep0, 8byte */
 167 #define EPEN_CNAK_EP0_8 (DEPCTL_EPENA|DEPCTL_CNAK|(CONTROL_EP<<11)|(3<<0))
 168
 169 /* DIEPCTLn/DOEPCTLn */
 170 #define BACK2BACK_SETUP_RECEIVED        (0x1<<6)
 171 #define INTKN_TXFEMP                    (0x1<<4)
 172 #define NON_ISO_IN_EP_TIMEOUT           (0x1<<3)
 173 #define CTRL_OUT_EP_SETUP_PHASE_DONE    (0x1<<3)
 174 #define AHB_ERROR                       (0x1<<2)
 175 #define TRANSFER_DONE                   (0x1<<0)
 176
 177 /* codes representing languages */
 178 const u8 string_desc0[] = {
 179         4, STRING_DESCRIPTOR, LANGID_US_L, LANGID_US_H,
 180 };
 181
 182 #ifdef CONFIG_SAMSUNG_USB
 183 const u8 string_desc1[] =       /* Manufacturer */
 184 {
 185         (0x14 + 2), STRING_DESCRIPTOR,
 186         'S', 0x0, '/', 0x0, 'W', 0x0, ' ', 0x0, 'C', 0x0,
 187         'e', 0x0, 'n', 0x0, 't', 0x0, 'e', 0x0, 'r', 0x0,
 188 };
 189 #else
 190 const u8 string_desc1[] =       /* Manufacturer */
 191 {
 192         (0x14 + 2), STRING_DESCRIPTOR,
 193         'S', 0x0, 'y', 0x0, 's', 0x0, 't', 0x0, 'e', 0x0,
 194         'm', 0x0, ' ', 0x0, 'M', 0x0, 'C', 0x0, 'U', 0x0,
 195 };
 196 #endif
 197
 198 #ifdef CONFIG_SAMSUNG_USB
 199 const u8 string_desc2[] =       /* Product */
 200 {
 201         (0x22 + 2), STRING_DESCRIPTOR,
 202         'S', 0x0, 'A', 0x0, 'M', 0x0, 'S', 0x0, 'U', 0x0,
 203         'N', 0x0, 'G', 0x0, ' ', 0x0, 'X', 0x0, 'O', 0x0,
 204         ' ', 0x0, 'D', 0x0, 'R', 0x0, 'I', 0x0, 'V', 0x0,
 205         'E', 0x0, 'R', 0x0
 206 };
 207 #else
 208 const u8 string_desc2[] =       /* Product */
 209 {
 210         (0x2a + 2), STRING_DESCRIPTOR,
 211         'S', 0x0, 'E', 0x0, 'C', 0x0, ' ', 0x0, 'S', 0x0,
 212         '3', 0x0, 'C', 0x0, '6', 0x0, '4', 0x0, '0', 0x0,
 213         '0', 0x0, 'X', 0x0, ' ', 0x0, 'T', 0x0, 'e', 0x0,
 214         's', 0x0, 't', 0x0, ' ', 0x0, 'B', 0x0, '/', 0x0,
 215         'D', 0x0
 216 };
 217 #endif
 218
 219 /* setting the device qualifier descriptor and a string descriptor */
 220 const u8 qualifier_desc[] = {
 221         0x0a,           /*  0 desc size */
 222         0x06,           /*  1 desc type (DEVICE_QUALIFIER) */
 223         0x00,           /*  2 USB release */
 224         0x02,           /*  3 => 2.00 */
 225         0xFF,           /*  4 class */
 226         0x00,           /*  5 subclass */
 227         0x00,           /*  6 protocol */
 228         64,             /*  7 max pack size */
 229         0x01,           /*  8 number of other-speed configuration */
 230         0x00,           /*  9 reserved */
 231 };
 232
 233 const u8 config_full[] = {
 234         0x09,           /*  0 desc size */
 235         0x07,           /*  1 desc type (other speed) */
 236         0x20,           /*  2 Total length of data returned */
 237         0x00,           /*  3 */
 238         0x01,           /*  4 Number of interfaces */
 239         0x01,           /*  5 value to use to select configuration */
 240         0x00,           /*  6 index of string desc */
 241         /*  7 same as configuration desc */
 242         CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED,
 243         0x19,           /*  8 same as configuration desc */
 244
 245 };
 246
 247 const u8 config_full_total[] = {
 248         0x09, 0x07, 0x20, 0x00, 0x01, 0x01, 0x00, 0xC0, 0x19,
 249         0x09, 0x04, 0x00, 0x00, 0x02, 0xff, 0x00, 0x00, 0x00,
 250         0x07, 0x05, 0x83, 0x02, 0x40, 0x00, 0x00,
 251         0x07, 0x05, 0x04, 0x02, 0x40, 0x00, 0x00
 252 };
 253
 254 const u8 config_high[] = {
 255         0x09,           /*  0 desc size */
 256         0x07,           /*  1 desc type (other speed) */
 257         0x20,           /*  2 Total length of data returned */
 258         0x00,           /*  3 */
 259         0x01,           /*  4 Number of interfaces */
 260         0x01,           /*  5 value to use to select configuration */
 261         0x00,           /*  6 index of string desc */
 262         /*  7 same as configuration desc */
 263         CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED,
 264         0x19,                   /*  8 same as configuration desc */
 265
 266 };
 267
 268 const u8 config_high_total[] = {
 269         0x09, 0x07, 0x20, 0x00, 0x01, 0x01, 0x00, 0xC0, 0x19,
 270         0x09, 0x04, 0x00, 0x00, 0x02, 0xff, 0x00, 0x00, 0x00,
 271         0x07, 0x05, 0x81, 0x02, 0x00, 0x02, 0x00,
 272         0x07, 0x05, 0x02, 0x02, 0x00, 0x02, 0x00
 273 };
 274
 275 /* Descriptor size */
 276 enum DESCRIPTOR_SIZE {
 277         DEVICE_DESC_SIZE = sizeof(device_desc_t),
 278         STRING_DESC0_SIZE = sizeof(string_desc0),
 279         STRING_DESC1_SIZE = sizeof(string_desc1),
 280         STRING_DESC2_SIZE = sizeof(string_desc2),
 281         CONFIG_DESC_SIZE = sizeof(config_desc_t),
 282         INTERFACE_DESC_SIZE = sizeof(intf_desc_t),
 283         ENDPOINT_DESC_SIZE = sizeof(ep_desc_t),
 284         DEVICE_QUALIFIER_SIZE = sizeof(qualifier_desc),
 285         OTHER_SPEED_CFG_SIZE = 9
 286 };
 287
 288 /*32 <cfg desc>+<if desc>+<endp0 desc>+<endp1 desc>*/
 289 #define CONFIG_DESC_TOTAL_SIZE  \
 290         (CONFIG_DESC_SIZE+INTERFACE_DESC_SIZE+ENDPOINT_DESC_SIZE*2)
 291
 292 static unsigned int phy_base;
 293 static unsigned int otg_base;
 294
 295 static inline void s5p_usb_init_base(void)
 296 {
 297         if (cpu_is_s5pc110()) {
 298                 phy_base = S5PC110_PHY_BASE;
 299                 otg_base = S5PC110_OTG_BASE;
 300         } else {
 301                 phy_base = S5PC100_PHY_BASE;
 302                 otg_base = S5PC100_OTG_BASE;
 303         }
 304 }
 305
 306 static inline int s5pc1xx_phy_read_reg(int offset)
 307 {
 308         return readl(phy_base + offset);
 309 }
 310
 311 static inline void s5pc1xx_phy_write_reg(int value, int offset)
 312 {
 313         writel(value, phy_base + offset);
 314 }
 315
 316 static inline int s5pc1xx_otg_read_reg(int offset)
 317 {
 318         return readl(otg_base + offset);
 319 }
 320
 321 static inline void s5pc1xx_otg_write_reg(int value, int offset)
 322 {
 323         writel(value, otg_base + offset);
 324 }
 325
 326 static void s5p_usb_init_phy(void)
 327 {
 328         if (cpu_is_s5pc110()) {
 329                 s5pc1xx_phy_write_reg(0xA0, OTG_PHYPWR);
 330                 s5pc1xx_phy_write_reg(0x3, OTG_PHYCTRL);
 331         } else {
 332                 s5pc1xx_phy_write_reg(0x0, OTG_PHYPWR);
 333 #ifdef CONFIG_OTG_CLK_OSCC
 334                 s5pc1xx_phy_write_reg(0x22, OTG_PHYCTRL);
 335 #else
 336                 s5pc1xx_phy_write_reg(0x2, OTG_PHYCTRL);
 337 #endif
 338         }
 339
 340         s5pc1xx_phy_write_reg(0x1, OTG_RSTCON);
 341         udelay(20);
 342         s5pc1xx_phy_write_reg(0x0, OTG_RSTCON);
 343         udelay(20);
 344 }
 345
 346 int s5p_usb_detect_irq(void)
 347 {
 348         u32 status;
 349         status = s5pc1xx_otg_read_reg(OTG_GINTSTS);
 350         return (status & 0x800c3810);
 351 }
 352
 353 void s5p_usb_clear_irq(void)
 354 {
 355         s5pc1xx_otg_write_reg(0xffffffff, OTG_GINTSTS);
 356 }
 357
 358 static void s5p_usb_core_soft_reset(void)
 359 {
 360         u32 tmp;
 361
 362         s5pc1xx_otg_write_reg(CORE_SOFT_RESET, OTG_GRSTCTL);
 363
 364         do {
 365                 tmp = s5pc1xx_otg_read_reg(OTG_GRSTCTL);
 366         } while (!(tmp & AHB_MASTER_IDLE));
 367 }
 368
 369 static void s5p_usb_wait_cable_insert(void)
 370 {
 371         u32 tmp;
 372         int ucFirst = 1;
 373
 374         do {
 375                 udelay(50);
 376
 377                 tmp = s5pc1xx_otg_read_reg(OTG_GOTGCTL);
 378
 379                 if (tmp & (B_SESSION_VALID | A_SESSION_VALID)) {
 380                         break;
 381                 } else if (ucFirst == 1) {
 382                         printf("Insert a OTG cable into the connector!\n");
 383                         ucFirst = 0;
 384                 }
 385         } while (1);
 386 }
 387
 388 static void s5p_usb_init_core(void)
 389 {
 390         s5pc1xx_otg_write_reg(PTXFE_HALF | NPTXFE_HALF | MODE_SLAVE |
 391                         BURST_SINGLE | GBL_INT_UNMASK, OTG_GAHBCFG);
 392
 393         s5pc1xx_otg_write_reg(
 394                  0x0 << 15      /* PHY Low Power Clock sel */
 395                | 0x1 << 14      /* Non-Periodic TxFIFO Rewind Enable */
 396                | 0x5 << 10      /* Turnaround time */
 397                | 0x0 << 9       /* 0:HNP disable, 1:HNP enable */
 398                | 0x0 << 8       /* 0:SRP disable, 1:SRP enable */
 399                | 0x0 << 7       /* ULPI DDR sel */
 400                | 0x0 << 6       /* 0: high speed utmi+, 1: full speed serial */
 401                | 0x0 << 4       /* 0: utmi+, 1:ulpi */
 402                | 0x1 << 3       /* phy i/f  0:8bit, 1:16bit */
 403                | 0x7 << 0,      /* HS/FS Timeout* */
 404                OTG_GUSBCFG);
 405 }
 406
 407 static void s5p_usb_check_current_mode(u8 *pucMode)
 408 {
 409         u32 tmp;
 410
 411         tmp = s5pc1xx_otg_read_reg(OTG_GINTSTS);
 412         *pucMode = tmp & 0x1;
 413 }
 414
 415 static void s5p_usb_soft_disconnect(int set)
 416 {
 417         u32 tmp;
 418
 419         tmp = s5pc1xx_otg_read_reg(OTG_DCTL);
 420         if (set)
 421                 tmp |= SOFT_DISCONNECT;
 422         else
 423                 tmp &= ~SOFT_DISCONNECT;
 424         s5pc1xx_otg_write_reg(tmp, OTG_DCTL);
 425 }
 426
 427 static void s5p_usb_init_device(void)
 428 {
 429         s5pc1xx_otg_write_reg(1 << 18 | otg.speed << 0, OTG_DCFG);
 430
 431         s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
 432                         INT_ENUMDONE | INT_RESET | INT_SUSPEND |
 433                         INT_RX_FIFO_NOT_EMPTY, OTG_GINTMSK);
 434 }
 435
 436 int s5p_usbctl_init(void)
 437 {
 438         u8 ucMode;
 439         u32 reg;
 440
 441         s5p_usb_init_base();
 442
 443         if (cpu_is_s5pc110()) {
 444                 reg = readl(S5PC110_USB_PHY_CON);
 445                 reg |= (1 << 0); /* USB PHY0 enable */
 446                 writel(reg, S5PC110_USB_PHY_CON);
 447         } else {
 448                 reg = readl(S5PC100_OTHERS);
 449                 reg |= (1 << 16); /* unmask usb signal */
 450                 writel(reg, S5PC100_OTHERS);
 451         }
 452
 453         otg.speed = speed;
 454         otg.set_config = 0;
 455         otg.ep0_state = EP0_STATE_INIT;
 456         otg.ep0_substate = 0;
 457
 458         s5p_usb_init_phy();
 459         s5p_usb_core_soft_reset();
 460         s5p_usb_wait_cable_insert();
 461         s5p_usb_init_core();
 462         s5p_usb_check_current_mode(&ucMode);
 463
 464         if (ucMode == INT_DEV_MODE) {
 465                 s5p_usb_soft_disconnect(1);
 466                 udelay(10);
 467                 s5p_usb_soft_disconnect(0);
 468                 s5p_usb_init_device();
 469                 return 0;
 470         } else {
 471                 printf("Error : Current Mode is Host\n");
 472                 return 0;
 473         }
 474 }
 475
 476 int s5p_usbc_activate(void)
 477 {
 478         return 0;
 479 }
 480
 481 void s5p_usb_stop(void)
 482 {
 483 }
 484
 485 static void s5p_usb_set_inep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize)
 486 {
 487         if (type == EP_TYPE_CONTROL) {
 488                 s5pc1xx_otg_write_reg((pktcnt << 19) | (xfersize << 0),
 489                                 OTG_DIEPTSIZ0);
 490         } else if (type == EP_TYPE_BULK) {
 491                 s5pc1xx_otg_write_reg((1 << 29) | (pktcnt << 19) |
 492                                 (xfersize << 0), OTG_DIEPTSIZ_IN);
 493         }
 494 }
 495
 496 static void s5p_usb_set_outep_xfersize(EP_TYPE type, u32 pktcnt, u32 xfersize)
 497 {
 498         if (type == EP_TYPE_CONTROL) {
 499                 s5pc1xx_otg_write_reg((1 << 29) | (pktcnt << 19) |
 500                                 (xfersize << 0), OTG_DOEPTSIZ0);
 501         } else if (type == EP_TYPE_BULK) {
 502                 s5pc1xx_otg_write_reg((pktcnt << 19) | (xfersize << 0),
 503                                 OTG_DOEPTSIZ_OUT);
 504         }
 505 }
 506
 507 /* works on both aligned and unaligned buffers */
 508 static void s5p_usb_write_ep0_fifo(u8 *buf, int num)
 509 {
 510         int i;
 511         u32 Wr_Data = 0;
 512
 513         for (i = 0; i < num; i += 4) {
 514                 Wr_Data = ((*(buf + 3)) << 24) |
 515                         ((*(buf + 2)) << 16) |
 516                         ((*(buf + 1)) << 8) |
 517                         *buf;
 518                 s5pc1xx_otg_write_reg(Wr_Data, OTG_EP0_FIFO);
 519                 buf += 4;
 520         }
 521 }
 522
 523 /* optimized fifo access routines, warning: only aligned buffers are supported */
 524 static inline void s5p_usb_write_in_fifo(u8 *buf, int num)
 525 {
 526         u32 fifo = otg_base + OTG_IN_FIFO;
 527         u32 *p = (u32 *)buf;
 528         int i;
 529
 530         for (i = 0; i < num; i += 4)
 531                 writel(*p++, fifo);
 532 }
 533
 534 static inline void s5p_usb_read_out_fifo(u8 *buf, int num)
 535 {
 536         u32 fifo = otg_base + OTG_OUT_FIFO;
 537         u32 *p = (u32 *)buf;
 538         int i;
 539
 540         for (i = 0; i < num; i += 4)
 541                 *p++ = readl(fifo);
 542 }
 543
 544 static void s5p_usb_get_desc(void)
 545 {
 546         switch (otg.dev_req.wValue_H) {
 547         case DEVICE_DESCRIPTOR:
 548                 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
 549                                 otg.dev_req.wLength_L);
 550                 otg.ep0_state = EP0_STATE_GD_DEV_0;
 551                 break;
 552
 553         case CONFIGURATION_DESCRIPTOR:
 554                 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
 555                                 otg.dev_req.wLength_L);
 556
 557                 if (otg.req_length > CONFIG_DESC_SIZE)
 558                         otg.ep0_state = EP0_STATE_GD_CFG_0;
 559                 else
 560                         otg.ep0_state = EP0_STATE_GD_CFG_ONLY_0;
 561                 break;
 562
 563         case STRING_DESCRIPTOR:
 564                 switch (otg.dev_req.wValue_L) {
 565                 case 0:
 566                         otg.ep0_state = EP0_STATE_GD_STR_I0;
 567                         break;
 568                 case 1:
 569                         otg.ep0_state = EP0_STATE_GD_STR_I1;
 570                         break;
 571                 case 2:
 572                         otg.ep0_state = EP0_STATE_GD_STR_I2;
 573                         break;
 574                 default:
 575                         break;
 576                 }
 577                 break;
 578
 579         case ENDPOINT_DESCRIPTOR:
 580                 switch (otg.dev_req.wValue_L & 0xf) {
 581                 case 0:
 582                         otg.ep0_state = EP0_STATE_GD_EP0_ONLY_0;
 583                         break;
 584                 case 1:
 585                         otg.ep0_state = EP0_STATE_GD_EP1_ONLY_0;
 586                         break;
 587                 default:
 588                         break;
 589                 }
 590                 break;
 591
 592         case DEVICE_QUALIFIER:
 593                 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
 594                                 otg.dev_req.wLength_L);
 595                 otg.ep0_state = EP0_STATE_GD_DEV_QUALIFIER;
 596                 break;
 597
 598         case OTHER_SPEED_CONFIGURATION:
 599                 otg.req_length = (u32)((otg.dev_req.wLength_H << 8) |
 600                                 otg.dev_req.wLength_L);
 601                 otg.ep0_state = EP0_STATE_GD_OTHER_SPEED;
 602                 break;
 603         }
 604 }
 605
 606 static void s5p_usb_clear_feature(void)
 607 {
 608         switch (otg.dev_req.bmRequestType) {
 609         case DEVICE_RECIPIENT:
 610                 if (otg.dev_req.wValue_L == 1)
 611                         remode_wakeup = 0;
 612                 break;
 613
 614         case ENDPOINT_RECIPIENT:
 615                 if (otg.dev_req.wValue_L == 0) {
 616                         if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
 617                                 get_status.ep_ctrl = 0;
 618
 619                         /* IN Endpoint */
 620                         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
 621                                 get_status.ep_in = 0;
 622
 623                         /* OUT Endpoint */
 624                         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
 625                                 get_status.ep_out = 0;
 626                 }
 627                 break;
 628
 629         default:
 630                 break;
 631         }
 632         otg.ep0_state = EP0_STATE_INIT;
 633 }
 634
 635 static void s5p_usb_set_feature(void)
 636 {
 637         switch (otg.dev_req.bmRequestType) {
 638         case DEVICE_RECIPIENT:
 639                 if (otg.dev_req.wValue_L == 1)
 640                         remode_wakeup = 1;
 641                 break;
 642
 643         case ENDPOINT_RECIPIENT:
 644                 if (otg.dev_req.wValue_L == 0) {
 645                         if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
 646                                 get_status.ep_ctrl = 1;
 647
 648                         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
 649                                 get_status.ep_in = 1;
 650
 651                         if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
 652                                 get_status.ep_out = 1;
 653                 }
 654                 break;
 655
 656         default:
 657                 break;
 658         }
 659
 660         switch (otg.dev_req.wValue_L) {
 661         case EP_STALL:
 662                 /* TBD: additional processing if required */
 663                 break;
 664
 665         case TEST_MODE:
 666                 /* not support */
 667                 break;
 668
 669         default:
 670                 break;
 671         }
 672         otg.ep0_state = EP0_STATE_INIT;
 673 }
 674
 675 static void s5p_usb_get_status(void)
 676 {
 677         switch (otg.dev_req.bmRequestType) {
 678         case (0x80):    /*device */
 679                 get_status.Device = ((u8) remode_wakeup << 1) | 0x1;
 680                 otg.ep0_state = EP0_STATE_GET_STATUS0;
 681                 break;
 682
 683         case (0x81):    /*interface */
 684                 get_status.Interface = 0;
 685                 otg.ep0_state = EP0_STATE_GET_STATUS1;
 686                 break;
 687
 688         case (0x82):    /*endpoint */
 689                 if ((otg.dev_req.wIndex_L & 0x7f) == CONTROL_EP)
 690                         otg.ep0_state = EP0_STATE_GET_STATUS2;
 691
 692                 if ((otg.dev_req.wIndex_L & 0x7f) == BULK_IN_EP)
 693                         otg.ep0_state = EP0_STATE_GET_STATUS3;
 694
 695                 if ((otg.dev_req.wIndex_L & 0x7f) == BULK_OUT_EP)
 696                         otg.ep0_state = EP0_STATE_GET_STATUS4;
 697                 break;
 698
 699         default:
 700                 break;
 701         }
 702 }
 703
 704 static void s5p_usb_ep0_int_hndlr(void)
 705 {
 706         u16 i;
 707         u32 buf[2] = {0x0000, };
 708         u16 addr;
 709
 710         if (otg.ep0_state == EP0_STATE_INIT) {
 711                 for (i = 0; i < 2; i++)
 712                         buf[i] = s5pc1xx_otg_read_reg(OTG_EP0_FIFO);
 713
 714                 otg.dev_req.bmRequestType = buf[0];
 715                 otg.dev_req.bRequest = buf[0] >> 8;
 716                 otg.dev_req.wValue_L = buf[0] >> 16;
 717                 otg.dev_req.wValue_H = buf[0] >> 24;
 718                 otg.dev_req.wIndex_L = buf[1];
 719                 otg.dev_req.wIndex_H = buf[1] >> 8;
 720                 otg.dev_req.wLength_L = buf[1] >> 16;
 721                 otg.dev_req.wLength_H = buf[1] >> 24;
 722
 723                 switch (otg.dev_req.bRequest) {
 724                 case STANDARD_SET_ADDRESS:
 725                         /* Set Address Update bit */
 726                         addr = (otg.dev_req.wValue_L);
 727                         s5pc1xx_otg_write_reg(1 << 18 | addr << 4 | otg.speed << 0,
 728                                OTG_DCFG);
 729                         otg.ep0_state = EP0_STATE_INIT;
 730                         break;
 731
 732                 case STANDARD_SET_DESCRIPTOR:
 733                         break;
 734
 735                 case STANDARD_SET_CONFIGURATION:
 736                         /* Configuration value in configuration descriptor */
 737                         config_value = otg.dev_req.wValue_L;
 738                         otg.set_config = 1;
 739                         otg.ep0_state = EP0_STATE_INIT;
 740
 741                         s5p_usb_connected = 1;
 742                         break;
 743
 744                 case STANDARD_GET_CONFIGURATION:
 745                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
 746
 747                         /*ep0 enable, clear nak, next ep0, 8byte */
 748                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 749                         s5pc1xx_otg_write_reg(config_value, OTG_EP0_FIFO);
 750                         otg.ep0_state = EP0_STATE_INIT;
 751                         break;
 752
 753                 case STANDARD_GET_DESCRIPTOR:
 754                         s5p_usb_get_desc();
 755                         break;
 756
 757                 case STANDARD_CLEAR_FEATURE:
 758                         s5p_usb_clear_feature();
 759                         break;
 760
 761                 case STANDARD_SET_FEATURE:
 762                         s5p_usb_set_feature();
 763                         break;
 764
 765                 case STANDARD_GET_STATUS:
 766                         s5p_usb_get_status();
 767                         break;
 768
 769                 case STANDARD_GET_INTERFACE:
 770                         otg.ep0_state = EP0_STATE_INTERFACE_GET;
 771                         break;
 772
 773                 case STANDARD_SET_INTERFACE:
 774                         get_intf.AlternateSetting = otg.dev_req.wValue_L;
 775                         otg.ep0_state = EP0_STATE_INIT;
 776                         break;
 777
 778                 case STANDARD_SYNCH_FRAME:
 779                         otg.ep0_state = EP0_STATE_INIT;
 780                         break;
 781
 782                 default:
 783                         break;
 784                 }
 785         }
 786
 787         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, otg.ctrl_max_pktsize);
 788
 789         /*clear nak, next ep0, 64byte */
 790         s5pc1xx_otg_write_reg(((1 << 26) | (CONTROL_EP << 11) | (0 << 0)),
 791                         OTG_DIEPCTL0);
 792 }
 793
 794 static void s5p_usb_set_otherspeed_conf_desc(u32 length)
 795 {
 796         /* Standard device descriptor */
 797         if (length == 9) {
 798                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 9);
 799                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 800                 s5p_usb_write_ep0_fifo((u8 *) &config_full, 9);
 801         } else if (length == 32) {
 802                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 32);
 803                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 804                 s5p_usb_write_ep0_fifo((u8 *) &config_full_total, 32);
 805         }
 806         otg.ep0_state = EP0_STATE_INIT;
 807 }
 808
 809 static void s5p_usb_transfer_ep0(void)
 810 {
 811         switch (otg.ep0_state) {
 812         case EP0_STATE_INIT:
 813                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 0);
 814
 815                 /*ep0 enable, clear nak, next ep0, 8byte */
 816                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 817                 break;
 818
 819         case EP0_STATE_GD_DEV_0:
 820                 /*ep0 enable, clear nak, next ep0, max 64byte */
 821                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 822                 if (otg.req_length < DEVICE_DESC_SIZE) {
 823                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 824                                         otg.req_length);
 825                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)),
 826                                         otg.req_length);
 827                 } else {
 828                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 829                                         DEVICE_DESC_SIZE);
 830                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)),
 831                                         DEVICE_DESC_SIZE);
 832                 }
 833                 otg.ep0_state = EP0_STATE_INIT;
 834                 break;
 835
 836         case EP0_STATE_GD_DEV_1:
 837                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 838                 if (otg.req_length < (2 * FS_CTRL_PKT_SIZE)) {
 839                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
 840                                         FS_CTRL_PKT_SIZE,
 841                                         otg.req_length - FS_CTRL_PKT_SIZE);
 842                         otg.ep0_state = EP0_STATE_INIT;
 843                 } else {
 844                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
 845                                         FS_CTRL_PKT_SIZE, FS_CTRL_PKT_SIZE);
 846                         otg.ep0_state = EP0_STATE_GD_DEV_2;
 847                 }
 848                 break;
 849
 850         case EP0_STATE_GD_DEV_2:
 851                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 852                 if (otg.req_length < DEVICE_DESC_SIZE) {
 853                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
 854                                         (2 * FS_CTRL_PKT_SIZE),
 855                                         otg.req_length - 2 * FS_CTRL_PKT_SIZE);
 856                 } else {
 857                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.dev)) +
 858                                         (2 * FS_CTRL_PKT_SIZE),
 859                                         DEVICE_DESC_SIZE - 2 * FS_CTRL_PKT_SIZE);
 860                 }
 861                 otg.ep0_state = EP0_STATE_INIT;
 862                 break;
 863
 864         case EP0_STATE_GD_CFG_0:
 865                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 866                 if (otg.req_length < CONFIG_DESC_TOTAL_SIZE) {
 867                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 868                                         otg.req_length);
 869                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
 870                                         otg.req_length);
 871                 } else {
 872                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 873                                         CONFIG_DESC_TOTAL_SIZE);
 874                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
 875                                         CONFIG_DESC_TOTAL_SIZE);
 876                 }
 877                 otg.ep0_state = EP0_STATE_INIT;
 878                 break;
 879
 880         case EP0_STATE_GD_CFG_1:
 881                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 882                 if (otg.req_length < (2 * FS_CTRL_PKT_SIZE)) {
 883                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 884                                         FS_CTRL_PKT_SIZE,
 885                                         (otg.req_length - FS_CTRL_PKT_SIZE));
 886                         otg.ep0_state = EP0_STATE_INIT;
 887                 } else {
 888                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 889                                         FS_CTRL_PKT_SIZE, FS_CTRL_PKT_SIZE);
 890                         otg.ep0_state = EP0_STATE_GD_CFG_2;
 891                 }
 892                 break;
 893
 894         case EP0_STATE_GD_CFG_2:
 895                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 896                 if (otg.req_length < (3 * FS_CTRL_PKT_SIZE)) {
 897                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 898                                         (2 * FS_CTRL_PKT_SIZE),
 899                                         otg.req_length - 2 * FS_CTRL_PKT_SIZE);
 900                         otg.ep0_state = EP0_STATE_INIT;
 901                 } else {
 902                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 903                                         (2 * FS_CTRL_PKT_SIZE), FS_CTRL_PKT_SIZE);
 904                         otg.ep0_state = EP0_STATE_GD_CFG_3;
 905                 }
 906                 break;
 907
 908         case EP0_STATE_GD_CFG_3:
 909                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 910                 if (otg.req_length < (4 * FS_CTRL_PKT_SIZE)) {
 911                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 912                                         (3 * FS_CTRL_PKT_SIZE),
 913                                         otg.req_length - 3 * FS_CTRL_PKT_SIZE);
 914                         otg.ep0_state = EP0_STATE_INIT;
 915                 } else {
 916                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 917                                         (3 * FS_CTRL_PKT_SIZE), FS_CTRL_PKT_SIZE);
 918                         otg.ep0_state = EP0_STATE_GD_CFG_4;
 919                 }
 920                 break;
 921
 922         case EP0_STATE_GD_CFG_4:
 923                 otg.ep0_state = EP0_STATE_INIT;
 924                 break;
 925
 926         case EP0_STATE_GD_DEV_QUALIFIER:
 927                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 928                 if (otg.req_length < 10) {
 929                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 930                                         otg.req_length);
 931                         s5p_usb_write_ep0_fifo((u8 *)qualifier_desc,
 932                                         otg.req_length);
 933                 } else {
 934                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 10);
 935                         s5p_usb_write_ep0_fifo((u8 *)qualifier_desc, 10);
 936                 }
 937                 otg.ep0_state = EP0_STATE_INIT;
 938                 break;
 939
 940         case EP0_STATE_GD_OTHER_SPEED:
 941                 s5p_usb_set_otherspeed_conf_desc(otg.req_length);
 942                 break;
 943
 944         case EP0_STATE_GD_OTHER_SPEED_HIGH_1:
 945                 if (otg.req_length == 9) {
 946                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
 947                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 948                         s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 8, 1);
 949                         otg.ep0_state = EP0_STATE_INIT;
 950                 } else {
 951                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
 952                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 953                         s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 8, 8);
 954                         otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_2;
 955                 }
 956                 break;
 957
 958         case EP0_STATE_GD_OTHER_SPEED_HIGH_2:
 959                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
 960                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 961                 s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 16, 8);
 962                 otg.ep0_state = EP0_STATE_GD_OTHER_SPEED_HIGH_3;
 963                 break;
 964
 965         case EP0_STATE_GD_OTHER_SPEED_HIGH_3:
 966                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 8);
 967                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 968                 s5p_usb_write_ep0_fifo(((u8 *) &config_high) + 24, 8);
 969                 otg.ep0_state = EP0_STATE_INIT;
 970                 break;
 971
 972         case EP0_STATE_GD_CFG_ONLY_0:
 973                 if (otg.req_length < CONFIG_DESC_SIZE) {
 974                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 975                                         otg.req_length);
 976                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 977                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
 978                                         otg.req_length);
 979                 } else {
 980                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
 981                                         CONFIG_DESC_SIZE);
 982                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
 983                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)),
 984                                         CONFIG_DESC_SIZE);
 985                 }
 986                 otg.ep0_state = EP0_STATE_INIT;
 987                 break;
 988
 989         case EP0_STATE_GD_CFG_ONLY_1:
 990                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
 991                 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.config)) +
 992                                 FS_CTRL_PKT_SIZE,
 993                                 CONFIG_DESC_SIZE - FS_CTRL_PKT_SIZE);
 994                 otg.ep0_state = EP0_STATE_INIT;
 995                 break;
 996
 997         case EP0_STATE_GD_IF_ONLY_0:
 998                 if (otg.req_length < INTERFACE_DESC_SIZE) {
 999                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
1000                                         otg.req_length);
1001                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1002                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.intf)),
1003                                         otg.req_length);
1004                 } else {
1005                         s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1,
1006                                         INTERFACE_DESC_SIZE);
1007                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1008                         s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.intf)),
1009                                         INTERFACE_DESC_SIZE);
1010                 }
1011                 otg.ep0_state = EP0_STATE_INIT;
1012                 break;
1013
1014         case EP0_STATE_GD_IF_ONLY_1:
1015                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1016                 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.intf)) +
1017                                 FS_CTRL_PKT_SIZE,
1018                                 INTERFACE_DESC_SIZE - FS_CTRL_PKT_SIZE);
1019                 otg.ep0_state = EP0_STATE_INIT;
1020                 break;
1021
1022         case EP0_STATE_GD_EP0_ONLY_0:
1023                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1024                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, ENDPOINT_DESC_SIZE);
1025                 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.ep1)),
1026                                 ENDPOINT_DESC_SIZE);
1027                 otg.ep0_state = EP0_STATE_INIT;
1028                 break;
1029
1030         case EP0_STATE_GD_EP1_ONLY_0:
1031                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, ENDPOINT_DESC_SIZE);
1032                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1033                 s5p_usb_write_ep0_fifo(((u8 *) &(otg.desc.ep2)),
1034                                 ENDPOINT_DESC_SIZE);
1035                 otg.ep0_state = EP0_STATE_INIT;
1036                 break;
1037
1038         case EP0_STATE_GD_STR_I0:
1039                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, STRING_DESC0_SIZE);
1040                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1041                 s5p_usb_write_ep0_fifo((u8 *)string_desc0, STRING_DESC0_SIZE);
1042                 otg.ep0_state = EP0_STATE_INIT;
1043                 break;
1044
1045         case EP0_STATE_GD_STR_I1:
1046                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, sizeof(string_desc1));
1047                 if ((otg.ep0_substate * otg.ctrl_max_pktsize +
1048                         otg.ctrl_max_pktsize) < sizeof(string_desc1)) {
1049                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1050
1051                         s5p_usb_write_ep0_fifo((u8 *)string_desc1 +
1052                                         (otg.ep0_substate * otg.ctrl_max_pktsize),
1053                                         otg.ctrl_max_pktsize);
1054                         otg.ep0_state = EP0_STATE_GD_STR_I1;
1055                         otg.ep0_substate++;
1056                 } else {
1057                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1058
1059                         s5p_usb_write_ep0_fifo((u8 *)string_desc1 +
1060                                         (otg.ep0_substate * otg.ctrl_max_pktsize),
1061                                         sizeof(string_desc1) - (otg.ep0_substate *
1062                                                 otg.ctrl_max_pktsize));
1063                         otg.ep0_state = EP0_STATE_INIT;
1064                         otg.ep0_substate = 0;
1065                 }
1066                 break;
1067
1068         case EP0_STATE_GD_STR_I2:
1069                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, sizeof(string_desc2));
1070                 if ((otg.ep0_substate * otg.ctrl_max_pktsize +
1071                         otg.ctrl_max_pktsize) < sizeof(string_desc2)) {
1072                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1073
1074                         s5p_usb_write_ep0_fifo((u8 *) string_desc2 +
1075                                         (otg.ep0_substate * otg.ctrl_max_pktsize),
1076                                         otg.ctrl_max_pktsize);
1077                         otg.ep0_state = EP0_STATE_GD_STR_I2;
1078                         otg.ep0_substate++;
1079                 } else {
1080                         s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_64, OTG_DIEPCTL0);
1081                         s5p_usb_write_ep0_fifo((u8 *) string_desc2 +
1082                                         (otg.ep0_substate * otg.ctrl_max_pktsize),
1083                                         sizeof(string_desc2) - (otg.ep0_substate *
1084                                                 otg.ctrl_max_pktsize));
1085                         otg.ep0_state = EP0_STATE_INIT;
1086                         otg.ep0_substate = 0;
1087                 }
1088                 break;
1089
1090         case EP0_STATE_INTERFACE_GET:
1091                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1092                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1093                 s5p_usb_write_ep0_fifo((u8 *) &get_intf, 1);
1094                 otg.ep0_state = EP0_STATE_INIT;
1095                 break;
1096
1097         case EP0_STATE_GET_STATUS0:
1098                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1099                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1100                 s5p_usb_write_ep0_fifo((u8 *) &get_status, 1);
1101                 otg.ep0_state = EP0_STATE_INIT;
1102                 break;
1103
1104         case EP0_STATE_GET_STATUS1:
1105                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1106                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1107                 s5p_usb_write_ep0_fifo((u8 *) &get_status + 1, 1);
1108                 otg.ep0_state = EP0_STATE_INIT;
1109                 break;
1110
1111         case EP0_STATE_GET_STATUS2:
1112                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1113                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1114                 s5p_usb_write_ep0_fifo((u8 *) &get_status + 2, 1);
1115                 otg.ep0_state = EP0_STATE_INIT;
1116                 break;
1117
1118         case EP0_STATE_GET_STATUS3:
1119                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1120                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1121                 s5p_usb_write_ep0_fifo((u8 *) &get_status + 3, 1);
1122                 otg.ep0_state = EP0_STATE_INIT;
1123                 break;
1124
1125         case EP0_STATE_GET_STATUS4:
1126                 s5p_usb_set_inep_xfersize(EP_TYPE_CONTROL, 1, 1);
1127                 s5pc1xx_otg_write_reg(EPEN_CNAK_EP0_8, OTG_DIEPCTL0);
1128                 s5p_usb_write_ep0_fifo((u8 *) &get_status + 4, 1);
1129                 otg.ep0_state = EP0_STATE_INIT;
1130                 break;
1131
1132         default:
1133                 break;
1134         }
1135 }
1136
1137 void s5p_usb_tx(char *tx_data, int tx_size)
1138 {
1139         otg.up_ptr = (u8 *) tx_data;
1140         otg.up_addr = (u32) tx_data;
1141         otg.up_size = tx_size;
1142
1143         if (otg.op_mode == USB_CPU) {
1144                 if (otg.up_size > otg.bulkin_max_pktsize) {
1145                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1,
1146                                         otg.bulkin_max_pktsize);
1147                 } else {
1148                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1, otg.up_size);
1149                 }
1150
1151                 /*ep1 enable, clear nak, bulk, usb active, max pkt */
1152                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1153                                 otg.bulkin_max_pktsize << 0, OTG_DIEPCTL_IN);
1154
1155                 s5p_usb_write_in_fifo(otg.up_ptr, otg.up_size);
1156         } else if ((otg.op_mode == USB_DMA) && (otg.up_size > 0)) {
1157                 u32 pktcnt, remainder;
1158
1159                 s5pc1xx_otg_write_reg(MODE_DMA | BURST_INCR4 | GBL_INT_UNMASK,
1160                                 OTG_GAHBCFG);
1161                 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1162                                 INT_ENUMDONE | INT_RESET | INT_SUSPEND,
1163                                 OTG_GINTMSK);
1164
1165                 s5pc1xx_otg_write_reg((u32) otg.up_ptr, OTG_DIEPDMA_IN);
1166
1167                 pktcnt = (u32) (otg.up_size / otg.bulkin_max_pktsize);
1168                 remainder = (u32) (otg.up_size % otg.bulkin_max_pktsize);
1169                 if (remainder != 0)
1170                         pktcnt += 1;
1171
1172                 if (pktcnt > 1023) {
1173                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1023,
1174                                         otg.bulkin_max_pktsize * 1023);
1175                 } else {
1176                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt,
1177                                         otg.up_size);
1178                 }
1179
1180                 /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */
1181                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1182                                 BULK_IN_EP << 11 | otg.bulkin_max_pktsize << 0,
1183                                 OTG_DIEPCTL_IN);
1184         }
1185 }
1186
1187 static void s5p_usb_rx(u32 fifo_cnt_byte)
1188 {
1189         if (otg.op_mode == USB_CPU) {
1190                 s5p_usb_read_out_fifo((u8 *)otg.dn_ptr, fifo_cnt_byte);
1191                 otg.dn_ptr += fifo_cnt_byte;
1192
1193                 s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1,
1194                                 otg.bulkout_max_pktsize);
1195
1196                 /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt */
1197                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1198                                 otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1199
1200                 if (((u32)otg.dn_ptr - otg.dn_addr) >= (otg.dn_filesize))
1201                         s5p_receive_done = 1;
1202         } else if (otg.dn_filesize > otg.bulkout_max_pktsize) {
1203                 u32 pkt_cnt, remain_cnt;
1204
1205                 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1206                                 INT_ENUMDONE | INT_RESET | INT_SUSPEND,
1207                                 OTG_GINTMSK);
1208                 s5pc1xx_otg_write_reg(MODE_DMA | BURST_INCR4 | GBL_INT_UNMASK,
1209                                 OTG_GAHBCFG);
1210                 s5pc1xx_otg_write_reg((u32) otg.dn_ptr, OTG_DOEPDMA_OUT);
1211                 pkt_cnt = (u32)(otg.dn_filesize - otg.bulkout_max_pktsize) /
1212                                 otg.bulkout_max_pktsize;
1213                 remain_cnt = (u32)((otg.dn_filesize - otg.bulkout_max_pktsize) %
1214                                 otg.bulkout_max_pktsize);
1215
1216                 if (remain_cnt != 0)
1217                         pkt_cnt += 1;
1218
1219                 if (pkt_cnt > 1023) {
1220                         s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1023,
1221                                         otg.bulkout_max_pktsize * 1023);
1222                 } else {
1223                         s5p_usb_set_outep_xfersize(EP_TYPE_BULK, pkt_cnt,
1224                                         otg.dn_filesize - otg.bulkout_max_pktsize);
1225                 }
1226
1227                 /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt */
1228                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1229                                 otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1230         }
1231 }
1232
1233 static void s5p_usb_int_bulkout(u32 fifo_cnt_byte)
1234 {
1235         s5p_usb_rx(fifo_cnt_byte);
1236 }
1237
1238 static void s5p_usb_dma_in_done(void)
1239 {
1240         s32 remain_cnt;
1241
1242         otg.up_ptr = (u8 *)s5pc1xx_otg_read_reg(OTG_DIEPDMA_IN);
1243         remain_cnt = otg.up_size - ((u32) otg.up_ptr - otg.up_addr);
1244
1245         if (remain_cnt > 0) {
1246                 u32 pktcnt, remainder;
1247                 pktcnt = (u32)(remain_cnt / otg.bulkin_max_pktsize);
1248                 remainder = (u32)(remain_cnt % otg.bulkin_max_pktsize);
1249
1250                 if (remainder != 0)
1251                         pktcnt += 1;
1252
1253                 if (pktcnt > 1023) {
1254                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1023,
1255                                         otg.bulkin_max_pktsize * 1023);
1256                 } else {
1257                         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, pktcnt,
1258                                         remain_cnt);
1259                 }
1260
1261                 /*ep1 enable, clear nak, bulk, usb active, next ep1, max pkt */
1262                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1263                                 BULK_IN_EP << 11 | otg.bulkin_max_pktsize << 0,
1264                                 OTG_DIEPCTL_IN);
1265
1266                 s5p_receive_done = 1;
1267         }
1268 }
1269
1270 static void s5p_usb_dma_out_done(void)
1271 {
1272         s32 remain_cnt;
1273
1274         otg.dn_ptr = (u8 *)s5pc1xx_otg_read_reg(OTG_DOEPDMA_OUT);
1275
1276         remain_cnt = otg.dn_filesize - ((u32) otg.dn_ptr - otg.dn_addr + 8);
1277
1278         if (remain_cnt > 0) {
1279                 u32 pktcnt, remainder;
1280                 pktcnt = (u32)(remain_cnt / otg.bulkout_max_pktsize);
1281                 remainder = (u32)(remain_cnt % otg.bulkout_max_pktsize);
1282
1283                 if (remainder != 0)
1284                         pktcnt += 1;
1285
1286                 if (pktcnt > 1023) {
1287                         s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1023,
1288                                         otg.bulkout_max_pktsize * 1023);
1289                 } else {
1290                         s5p_usb_set_outep_xfersize(EP_TYPE_BULK, pktcnt,
1291                                         remain_cnt);
1292                 }
1293
1294                 /*ep3 enable, clear nak, bulk, usb active, next ep3, max pkt 64 */
1295                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1296                                 otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1297         } else {
1298                 udelay(500);    /*for FPGA ??? */
1299         }
1300 }
1301
1302 static void s5p_usb_set_all_outep_nak(void)
1303 {
1304         u8 i;
1305         u32 tmp;
1306
1307         for (i = 0; i < 16; i++) {
1308                 tmp = s5pc1xx_otg_read_reg(OTG_DOEPCTL0 + 0x20 * i);
1309                 tmp |= DEPCTL_SNAK;
1310                 s5pc1xx_otg_write_reg(tmp, OTG_DOEPCTL0 + 0x20 * i);
1311         }
1312 }
1313
1314 static void s5p_usb_clear_all_outep_nak(void)
1315 {
1316         u8 i;
1317         u32 tmp;
1318
1319         for (i = 0; i < 16; i++) {
1320                 tmp = s5pc1xx_otg_read_reg(OTG_DOEPCTL0 + 0x20 * i);
1321                 tmp |= (DEPCTL_EPENA | DEPCTL_CNAK);
1322                 s5pc1xx_otg_write_reg(tmp, OTG_DOEPCTL0 + 0x20 * i);
1323         }
1324 }
1325
1326 static void s5p_usb_set_max_pktsize(USB_SPEED speed)
1327 {
1328         otg.speed = USB_HIGH;
1329         otg.ctrl_max_pktsize = HS_CTRL_PKT_SIZE;
1330         otg.bulkin_max_pktsize = HS_BULK_PKT_SIZE;
1331         otg.bulkout_max_pktsize = HS_BULK_PKT_SIZE;
1332 }
1333
1334 static void s5p_usb_set_endpoint(void)
1335 {
1336         /* Unmask OTG_DAINT source */
1337         s5pc1xx_otg_write_reg(0xff, OTG_DIEPINT0);
1338         s5pc1xx_otg_write_reg(0xff, OTG_DOEPINT0);
1339         s5pc1xx_otg_write_reg(0xff, OTG_DIEPINT_IN);
1340         s5pc1xx_otg_write_reg(0xff, OTG_DOEPINT_OUT);
1341
1342         /* Init For Ep0 */
1343         /*MPS:64bytes */
1344         s5pc1xx_otg_write_reg(((1 << 26) | (CONTROL_EP << 11) | (0 << 0)),
1345                         OTG_DIEPCTL0);
1346         /*ep0 enable, clear nak */
1347         s5pc1xx_otg_write_reg((1u << 31) | (1 << 26) | (0 << 0),
1348                         OTG_DOEPCTL0);
1349 }
1350
1351 static void s5p_usb_set_descriptors(void)
1352 {
1353 #if defined (CONFIG_SAMSUNG_USB)
1354         otg.desc.dev.bLength            = DEVICE_DESC_SIZE;
1355         otg.desc.dev.bDescriptorType    = DEVICE_DESCRIPTOR;
1356         otg.desc.dev.bDeviceClass       = 0xFF;
1357         otg.desc.dev.bDeviceSubClass    = 0x0;
1358         otg.desc.dev.bDeviceProtocol    = 0x0;
1359         otg.desc.dev.bMaxPacketSize0    = otg.ctrl_max_pktsize;
1360         otg.desc.dev.idVendorL          = 0xE8;
1361         otg.desc.dev.idVendorH          = 0x04;
1362         otg.desc.dev.idProductL         = 0x04;
1363         otg.desc.dev.idProductH         = 0x12;
1364         otg.desc.dev.iManufacturer      = 0x0;
1365         otg.desc.dev.iProduct           = 0x2;
1366         otg.desc.dev.iSerialNumber      = 0x0;
1367         otg.desc.dev.bNumConfigurations = 0x1;
1368         otg.desc.dev.bcdUSBL    = 0x00;
1369         otg.desc.dev.bcdUSBH    = 0x02;
1370
1371         otg.desc.config.bLength         = CONFIG_DESC_SIZE;
1372         otg.desc.config.bDescriptorType = CONFIGURATION_DESCRIPTOR;
1373         otg.desc.config.wTotalLengthL   = CONFIG_DESC_TOTAL_SIZE;
1374         otg.desc.config.wTotalLengthH   = 0;
1375         otg.desc.config.bNumInterfaces  = 1;
1376         otg.desc.config.bConfigurationValue = 1;
1377         otg.desc.config.iConfiguration  = 0;
1378         otg.desc.config.bmAttributes    = CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED;
1379         otg.desc.config.maxPower        = 50;
1380 #else
1381         otg.desc.dev.bLength            = DEVICE_DESC_SIZE;
1382         otg.desc.dev.bDescriptorType    = DEVICE_DESCRIPTOR;
1383         otg.desc.dev.bDeviceClass       = 0xFF;
1384         otg.desc.dev.bDeviceSubClass    = 0x0;
1385         otg.desc.dev.bDeviceProtocol    = 0x0;
1386         otg.desc.dev.bMaxPacketSize0    = otg.ctrl_max_pktsize;
1387         otg.desc.dev.idVendorL          = 0xE8;
1388         otg.desc.dev.idVendorH          = 0x04;
1389         otg.desc.dev.idProductL         = 0x34;
1390         otg.desc.dev.idProductH         = 0x12;
1391         otg.desc.dev.bcdDeviceL         = 0x00;
1392         otg.desc.dev.bcdDeviceH         = 0x01;
1393         otg.desc.dev.iManufacturer      = 0x1;
1394         otg.desc.dev.iProduct           = 0x2;
1395         otg.desc.dev.iSerialNumber      = 0x0;
1396         otg.desc.dev.bNumConfigurations = 0x1;
1397         otg.desc.dev.bcdUSBL    = 0x00;
1398         otg.desc.dev.bcdUSBH    = 0x02;
1399
1400         otg.desc.config.bLength         = CONFIG_DESC_SIZE;
1401         otg.desc.config.bDescriptorType = CONFIGURATION_DESCRIPTOR;
1402         otg.desc.config.wTotalLengthL   = CONFIG_DESC_TOTAL_SIZE;
1403         otg.desc.config.wTotalLengthH   = 0;
1404         otg.desc.config.bNumInterfaces  = 1;
1405         otg.desc.config.bConfigurationValue = 1;
1406         otg.desc.config.iConfiguration  = 0;
1407         otg.desc.config.bmAttributes    = CONF_ATTR_DEFAULT | CONF_ATTR_SELFPOWERED;
1408         otg.desc.config.maxPower        = 25;
1409 #endif
1410         otg.desc.intf.bLength           = INTERFACE_DESC_SIZE;
1411         otg.desc.intf.bDescriptorType   = INTERFACE_DESCRIPTOR;
1412         otg.desc.intf.bInterfaceNumber  = 0x0;
1413         otg.desc.intf.bAlternateSetting = 0x0;
1414         otg.desc.intf.bNumEndpoints     = 2;
1415         otg.desc.intf.bInterfaceClass   = 0xff;
1416         otg.desc.intf.bInterfaceSubClass = 0xff;
1417         otg.desc.intf.bInterfaceProtocol = 0xff;
1418         otg.desc.intf.iInterface        = 0x0;
1419
1420         otg.desc.ep1.bLength            = ENDPOINT_DESC_SIZE;
1421         otg.desc.ep1.bDescriptorType    = ENDPOINT_DESCRIPTOR;
1422         otg.desc.ep1.bEndpointAddress   = BULK_IN_EP | EP_ADDR_IN;
1423         otg.desc.ep1.bmAttributes       = EP_ATTR_BULK;
1424         otg.desc.ep1.wMaxPacketSizeL    = (u8)otg.bulkin_max_pktsize;
1425         otg.desc.ep1.wMaxPacketSizeH    = (u8)(otg.bulkin_max_pktsize >> 8);
1426         otg.desc.ep1.bInterval          = 0x0;
1427
1428         otg.desc.ep2.bLength            = ENDPOINT_DESC_SIZE;
1429         otg.desc.ep2.bDescriptorType    = ENDPOINT_DESCRIPTOR;
1430         otg.desc.ep2.bEndpointAddress   = BULK_OUT_EP | EP_ADDR_OUT;
1431         otg.desc.ep2.bmAttributes       = EP_ATTR_BULK;
1432         otg.desc.ep2.wMaxPacketSizeL    = (u8)otg.bulkout_max_pktsize;
1433         otg.desc.ep2.wMaxPacketSizeH    = (u8)(otg.bulkout_max_pktsize >> 8);
1434         otg.desc.ep2.bInterval          = 0x0;
1435 }
1436
1437 static void s5p_usb_set_opmode(USB_OPMODE mode)
1438 {
1439         otg.op_mode = mode;
1440
1441         s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP | INT_ENUMDONE |
1442                         INT_RESET | INT_SUSPEND | INT_RX_FIFO_NOT_EMPTY,
1443                         OTG_GINTMSK);
1444
1445         s5pc1xx_otg_write_reg(MODE_SLAVE | BURST_SINGLE | GBL_INT_UNMASK,
1446                         OTG_GAHBCFG);
1447
1448         s5p_usb_set_outep_xfersize(EP_TYPE_BULK, 1, otg.bulkout_max_pktsize);
1449         s5p_usb_set_inep_xfersize(EP_TYPE_BULK, 1, 0);
1450
1451         /*bulk out ep enable, clear nak, bulk, usb active, next ep3, max pkt */
1452         s5pc1xx_otg_write_reg(1u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1453                         otg.bulkout_max_pktsize << 0, OTG_DOEPCTL_OUT);
1454
1455         /*bulk in ep enable, clear nak, bulk, usb active, next ep1, max pkt */
1456         s5pc1xx_otg_write_reg(0u << 31 | 1 << 26 | 2 << 18 | 1 << 15 |
1457                         otg.bulkin_max_pktsize << 0, OTG_DIEPCTL_IN);
1458 }
1459
1460 static void s5p_usb_reset(void)
1461 {
1462         s5p_usb_set_all_outep_nak();
1463
1464         otg.ep0_state = EP0_STATE_INIT;
1465         s5pc1xx_otg_write_reg(((1 << BULK_OUT_EP) | (1 << CONTROL_EP)) << 16 |
1466                         ((1 << BULK_IN_EP) | (1 << CONTROL_EP)), OTG_DAINTMSK);
1467         s5pc1xx_otg_write_reg(CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR |
1468                         TRANSFER_DONE, OTG_DOEPMSK);
1469         s5pc1xx_otg_write_reg(INTKN_TXFEMP | NON_ISO_IN_EP_TIMEOUT | AHB_ERROR |
1470                         TRANSFER_DONE, OTG_DIEPMSK);
1471
1472         /* Rx FIFO Size */
1473         s5pc1xx_otg_write_reg(RX_FIFO_SIZE, OTG_GRXFSIZ);
1474
1475         /* Non Periodic Tx FIFO Size */
1476         s5pc1xx_otg_write_reg(NPTX_FIFO_SIZE << 16 | NPTX_FIFO_START_ADDR << 0,
1477                         OTG_GNPTXFSIZ);
1478
1479         s5p_usb_clear_all_outep_nak();
1480
1481         /*clear device address */
1482         s5pc1xx_otg_write_reg(s5pc1xx_otg_read_reg(OTG_DCFG) & ~(0x7f << 4),
1483                         OTG_DCFG);
1484 }
1485
1486 static int s5p_usb_set_init(void)
1487 {
1488         u32 status;
1489
1490         status = s5pc1xx_otg_read_reg(OTG_DSTS);
1491
1492         /* Set if Device is High speed or Full speed */
1493         if (((status & 0x6) >> 1) == USB_HIGH) {
1494                 s5p_usb_set_max_pktsize(USB_HIGH);
1495         } else if (((status & 0x6) >> 1) == USB_FULL) {
1496                 printf("Error: Don't support Full_Speed\n");
1497                 return 0;
1498         } else {
1499                 printf("Error: Neither High_Speed nor Full_Speed\n");
1500                 return 0;
1501         }
1502
1503         s5p_usb_set_endpoint();
1504         s5p_usb_set_descriptors();
1505         s5p_usb_set_opmode(op_mode);
1506
1507         return 1;
1508 }
1509
1510 static void s5p_usb_pkt_receive(void)
1511 {
1512         u32 rx_status;
1513         u32 fifo_cnt_byte;
1514
1515         rx_status = s5pc1xx_otg_read_reg(OTG_GRXSTSP);
1516
1517         if ((rx_status & (0xf << 17)) == SETUP_PKT_RECEIVED) {
1518                 s5p_usb_ep0_int_hndlr();
1519         } else if ((rx_status & (0xf << 17)) == OUT_PKT_RECEIVED) {
1520                 fifo_cnt_byte = (rx_status & 0x7ff0) >> 4;
1521
1522                 if ((rx_status & BULK_OUT_EP) && (fifo_cnt_byte)) {
1523                         s5p_usb_int_bulkout(fifo_cnt_byte);
1524                         if (otg.op_mode == USB_CPU) {
1525                                 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP |
1526                                         INT_IN_EP | INT_ENUMDONE | INT_RESET |
1527                                         INT_SUSPEND | INT_RX_FIFO_NOT_EMPTY,
1528                                         OTG_GINTMSK);
1529                         }
1530                         return;
1531                 }
1532
1533         } else if ((rx_status & (0xf << 17)) == GLOBAL_OUT_NAK) {
1534                 /* nop */
1535         } else if ((rx_status & (0xf << 17)) == OUT_TRNASFER_COMPLETED) {
1536                 /* nop */
1537         } else if ((rx_status & (0xf << 17)) == SETUP_TRANSACTION_COMPLETED) {
1538                 /* nop */
1539         } else {
1540                 /* nop */
1541         }
1542 }
1543
1544 static void s5p_usb_transfer(void)
1545 {
1546         u32 ep_int;
1547         u32 check_dma;
1548         u32 ep_int_status;
1549
1550         ep_int = s5pc1xx_otg_read_reg(OTG_DAINT);
1551
1552         if (ep_int & (1 << CONTROL_EP)) {
1553                 ep_int_status = s5pc1xx_otg_read_reg(OTG_DIEPINT0);
1554
1555                 if (ep_int_status & INTKN_TXFEMP) {
1556                         u32 uNTxFifoSpace;
1557                         do {
1558                                 uNTxFifoSpace = s5pc1xx_otg_read_reg(OTG_GNPTXSTS)
1559                                                 & 0xffff;
1560                         } while (uNTxFifoSpace < otg.ctrl_max_pktsize);
1561
1562                         s5p_usb_transfer_ep0();
1563                 }
1564
1565                 s5pc1xx_otg_write_reg(ep_int_status, OTG_DIEPINT0);
1566         }
1567
1568         if (ep_int & ((1 << CONTROL_EP) << 16)) {
1569                 ep_int_status = s5pc1xx_otg_read_reg(OTG_DOEPINT0);
1570
1571                 s5p_usb_set_outep_xfersize(EP_TYPE_CONTROL, 1, 8);
1572                 s5pc1xx_otg_write_reg(1u << 31 | 1 << 26, OTG_DOEPCTL0);
1573
1574                 s5pc1xx_otg_write_reg(ep_int_status, OTG_DOEPINT0);
1575         }
1576
1577         if (ep_int & (1 << BULK_IN_EP)) {
1578                 ep_int_status = s5pc1xx_otg_read_reg(OTG_DIEPINT_IN);
1579
1580                 s5pc1xx_otg_write_reg(ep_int_status, OTG_DIEPINT_IN);
1581                 check_dma = s5pc1xx_otg_read_reg(OTG_GAHBCFG);
1582
1583                 if ((check_dma & MODE_DMA) && (ep_int_status & TRANSFER_DONE))
1584                         s5p_usb_dma_in_done();
1585         }
1586
1587         if (ep_int & ((1 << BULK_OUT_EP) << 16)) {
1588                 ep_int_status = s5pc1xx_otg_read_reg(OTG_DOEPINT_OUT);
1589
1590                 s5pc1xx_otg_write_reg(ep_int_status, OTG_DOEPINT_OUT);
1591                 check_dma = s5pc1xx_otg_read_reg(OTG_GAHBCFG);
1592
1593                 if ((check_dma & MODE_DMA) && (ep_int_status & TRANSFER_DONE))
1594                         s5p_usb_dma_out_done();
1595         }
1596 }
1597
1598 void s5p_udc_int_hndlr(void)
1599 {
1600         u32 int_status;
1601         int tmp;
1602
1603         int_status = s5pc1xx_otg_read_reg(OTG_GINTSTS);
1604         s5pc1xx_otg_write_reg(int_status, OTG_GINTSTS);
1605
1606         if (int_status & INT_RESET) {
1607                 s5pc1xx_otg_write_reg(INT_RESET, OTG_GINTSTS);
1608                 s5p_usb_reset();
1609         }
1610
1611         if (int_status & INT_ENUMDONE) {
1612                 s5pc1xx_otg_write_reg(INT_ENUMDONE, OTG_GINTSTS);
1613
1614                 tmp = s5p_usb_set_init();
1615                 if (tmp == 0)
1616                         return;
1617         }
1618
1619         if (int_status & INT_RESUME)
1620                 s5pc1xx_otg_write_reg(INT_RESUME, OTG_GINTSTS);
1621
1622         if (int_status & INT_SUSPEND)
1623                 s5pc1xx_otg_write_reg(INT_SUSPEND, OTG_GINTSTS);
1624
1625         if (int_status & INT_RX_FIFO_NOT_EMPTY) {
1626                 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1627                                 INT_ENUMDONE | INT_RESET | INT_SUSPEND,
1628                                 OTG_GINTMSK);
1629
1630                 s5p_usb_pkt_receive();
1631
1632                 s5pc1xx_otg_write_reg(INT_RESUME | INT_OUT_EP | INT_IN_EP |
1633                                 INT_ENUMDONE | INT_RESET | INT_SUSPEND |
1634                                 INT_RX_FIFO_NOT_EMPTY, OTG_GINTMSK);
1635         }
1636
1637         if ((int_status & INT_IN_EP) || (int_status & INT_OUT_EP))
1638                 s5p_usb_transfer();
1639 }