3 * Common board functions for OMAP3 based boards.
5 * (C) Copyright 2004-2008
6 * Texas Instruments, <www.ti.com>
9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com>
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/arch/sys_proto.h>
38 #include <asm/arch/mem.h>
40 extern omap3_sysinfo sysinfo;
42 extern u32 is_mem_sdr(void);
44 /******************************************************************************
46 * Description: spinning delay to use before udelay works
47 *****************************************************************************/
48 static inline void delay(unsigned long loops)
50 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
51 "bne 1b":"=r" (loops):"0"(loops));
54 /******************************************************************************
55 * Routine: secure_unlock
56 * Description: Setup security registers for access
58 *****************************************************************************/
59 void secure_unlock_mem(void)
61 pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM;
62 pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM;
63 pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM;
64 pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM;
65 sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;
67 /* Protection Module Register Target APE (PM_RT) */
68 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
69 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
70 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
71 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
73 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
74 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
75 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
77 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
78 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
79 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
80 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
83 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
84 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
85 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
87 /* SDRC region 0 public */
88 writel(UNLOCK_1, &sms_base->rg_att0);
91 /******************************************************************************
92 * Routine: secureworld_exit()
93 * Description: If chip is EMU and boot type is external
94 * configure secure registers and exit secure world
96 *****************************************************************************/
97 void secureworld_exit()
101 /* configrue non-secure access control register */
102 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
103 /* enabling co-processor CP10 and CP11 accesses in NS world */
104 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
106 * allow allocation of locked TLBs and L2 lines in NS world
107 * allow use of PLE registers in NS world also
109 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
110 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
112 /* Enable ASA in ACR register */
113 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
114 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
115 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
117 /* Exiting secure world */
118 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
119 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
120 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
123 /******************************************************************************
124 * Routine: setup_auxcr()
125 * Description: Write to AuxCR desired value using SMI.
127 *****************************************************************************/
131 volatile unsigned int j;
132 /* Save r0, r12 and restore them after usage */
133 __asm__ __volatile__("mov %0, r12":"=r"(j));
134 __asm__ __volatile__("mov %0, r0":"=r"(i));
137 * GP Device ROM code API usage here
138 * r12 = AUXCR Write function and r0 value
140 __asm__ __volatile__("mov r12, #0x3");
141 __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
143 __asm__ __volatile__("orr r0, r0, #0x10");
145 __asm__ __volatile__("orr r0, r0, #1 << 5");
146 /* SMI instruction to call ROM Code API */
147 __asm__ __volatile__(".word 0xE1600070");
148 __asm__ __volatile__("mov r0, %0":"=r"(i));
149 __asm__ __volatile__("mov r12, %0":"=r"(j));
152 /******************************************************************************
153 * Routine: try_unlock_sram()
154 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
156 *****************************************************************************/
157 void try_unlock_memory()
160 int in_sdram = is_running_in_sdram();
163 * if GP device unlock device SRAM for general use
164 * secure code breaks for Secure/Emulation device - HS/E/T
166 mode = get_device_type();
167 if (mode == GP_DEVICE)
171 * If device is EMU and boot is XIP external booting
172 * Unlock firewalls and disable L2 and put chip
173 * out of secure world
175 * Assuming memories are unlocked by the demon who put us in SDRAM
177 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
186 /******************************************************************************
188 * Description: Does early system init of muxing and clocks.
189 * - Called path is with SRAM stack.
190 *****************************************************************************/
193 int in_sdram = is_running_in_sdram();
200 * Right now flushing at low MPU speed.
201 * Need to move after clock init
203 v7_flush_dcache_all(get_device_type());
204 #ifndef CONFIG_ICACHE_OFF
214 * Writing to AuxCR in U-boot using SMI for GP DEV
215 * Currently SMI in Kernel on ES2 devices seems to have an issue
216 * Once that is resolved, we can postpone this config to kernel
218 if (get_device_type() == GP_DEVICE)
232 /******************************************************************************
233 * Routine: wait_for_command_complete
234 * Description: Wait for posting to finish on watchdog
235 *****************************************************************************/
236 void wait_for_command_complete(watchdog_t *wd_base)
240 pending = readl(&wd_base->wwps);
244 /******************************************************************************
245 * Routine: watchdog_init
246 * Description: Shut down watch dogs
247 *****************************************************************************/
248 void watchdog_init(void)
250 watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;
251 prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
254 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
255 * either taken care of by ROM (HS/EMU) or not accessible (GP).
256 * We need to take care of WD2-MPU or take a PRCM reset. WD3
257 * should not be running and does not generate a PRCM reset.
260 sr32(&prcm_base->fclken_wkup, 5, 1, 1);
261 sr32(&prcm_base->iclken_wkup, 5, 1, 1);
262 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
264 writel(WD_UNLOCK1, &wd2_base->wspr);
265 wait_for_command_complete(wd2_base);
266 writel(WD_UNLOCK2, &wd2_base->wspr);
269 /******************************************************************************
271 * Description: sets uboots idea of sdram size
272 *****************************************************************************/
275 DECLARE_GLOBAL_DATA_PTR;
276 unsigned int size0 = 0, size1 = 0;
279 * If a second bank of DDR is attached to CS1 this is
280 * where it can be started. Early init code will init
283 if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
284 do_sdrc_init(CS1, NOT_EARLY);
285 make_cs1_contiguous();
288 size0 = get_sdr_cs_size(CS0);
289 size1 = get_sdr_cs_size(CS1);
291 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
292 gd->bd->bi_dram[0].size = size0;
293 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
294 gd->bd->bi_dram[1].size = size1;
299 /******************************************************************************
300 * Dummy function to handle errors for EABI incompatibility
301 *****************************************************************************/
306 /******************************************************************************
307 * Dummy function to handle errors for EABI incompatibility
308 *****************************************************************************/
313 #ifdef CONFIG_NAND_OMAP_GPMC
314 /******************************************************************************
315 * OMAP3 specific command to switch between NAND HW and SW ecc
316 *****************************************************************************/
317 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
321 if (strncmp(argv[1], "hw", 2) == 0)
322 omap_nand_switch_ecc(1);
323 else if (strncmp(argv[1], "sw", 2) == 0)
324 omap_nand_switch_ecc(0);
331 printf ("Usage: nandecc %s\n", cmdtp->usage);
336 nandecc, 2, 1, do_switch_ecc,
337 "nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
338 "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm\n"
341 #endif /* CONFIG_NAND_OMAP_GPMC */
343 #ifdef CONFIG_DISPLAY_BOARDINFO
345 * Print board information
347 int checkboard (void)
356 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
357 sysinfo.nand_string);
361 #endif /* CONFIG_DISPLAY_BOARDINFO */