2 * Power and Sleep Controller (PSC) functions.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
6 * Copyright (C) 2004 Texas Instruments.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <asm/arch/hardware.h>
30 * The PSC manages three inputs to a "module" which may be a peripheral or
31 * CPU. Those inputs are the module's: clock; reset signal; and sometimes
32 * its power domain. For our purposes, we only care whether clock and power
33 * are active, and the module is out of reset.
35 * DaVinci chips may include two separate power domains: "Always On" and "DSP".
36 * Chips without a DSP generally have only one domain.
38 * The "Always On" power domain is always on when the chip is on, and is
39 * powered by the VDD pins (on DM644X). The majority of DaVinci modules
40 * lie within the "Always On" power domain.
42 * A separate domain called the "DSP" domain houses the C64x+ and other video
43 * hardware such as VICP. In some chips, the "DSP" domain is not always on.
44 * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
47 /* Works on Always On power domain only (no PD argument) */
48 void lpsc_on(unsigned int id)
50 dv_reg_p mdstat, mdctl;
52 if (id >= DAVINCI_LPSC_GEM)
53 return; /* Don't work on DSP Power Domain */
55 mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
56 mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
58 while (REG(PSC_PTSTAT) & 0x01)
61 if ((*mdstat & 0x1f) == 0x03)
62 return; /* Already on and enabled */
67 #ifdef CONFIG_SOC_DM644X
68 /* Special treatment for some modules as for sprue14 p.7.4.2 */
69 case DAVINCI_LPSC_VPSSSLV:
70 case DAVINCI_LPSC_EMAC:
71 case DAVINCI_LPSC_EMAC_WRAPPER:
72 case DAVINCI_LPSC_MDIO:
73 case DAVINCI_LPSC_USB:
74 case DAVINCI_LPSC_ATA:
75 case DAVINCI_LPSC_VLYNQ:
76 case DAVINCI_LPSC_UHPI:
77 case DAVINCI_LPSC_DDR_EMIF:
78 case DAVINCI_LPSC_AEMIF:
79 case DAVINCI_LPSC_MMC_SD:
80 case DAVINCI_LPSC_MEMSTICK:
81 case DAVINCI_LPSC_McBSP:
82 case DAVINCI_LPSC_GPIO:
88 REG(PSC_PTCMD) = 0x01;
90 while (REG(PSC_PTSTAT) & 0x03)
92 while ((*mdstat & 0x1f) != 0x03) /* Probably an overkill... */
96 /* Not all DaVinci chips have a DSP power domain. */
97 #ifdef CONFIG_SOC_DM644X
99 /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
100 #if !defined(CONFIG_SYS_USE_DSPLINK)
105 if (REG(PSC_PDSTAT1) & 0x1f)
106 return; /* Already on */
108 REG(PSC_GBLCTL) |= 0x01;
109 REG(PSC_PDCTL1) |= 0x01;
110 REG(PSC_PDCTL1) &= ~0x100;
111 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
112 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
113 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
114 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
115 REG(PSC_PTCMD) = 0x02;
117 for (i = 0; i < 100; i++) {
118 if (REG(PSC_EPCPR) & 0x02)
122 REG(PSC_CHP_SHRTSW) = 0x01;
123 REG(PSC_PDCTL1) |= 0x100;
124 REG(PSC_EPCCR) = 0x02;
126 for (i = 0; i < 100; i++) {
127 if (!(REG(PSC_PTSTAT) & 0x02))
131 REG(PSC_GBLCTL) &= ~0x1f;
133 #endif /* CONFIG_SYS_USE_DSPLINK */
135 #endif /* have a DSP */