2 * Low-level board setup code for TI DaVinci SoC based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
8 * Made board specific defines such as DDR timing and PLL
9 * dividers. These should be set in the board config file
11 * Partially based on TI sources, original copyrights follow:
15 * Board specific setup info
18 * Texas Instruments, <www.ti.com>
19 * Kshitij Gupta <Kshitij@ti.com>
21 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
23 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
24 * See file CREDITS for list of people who contributed to this
27 * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
28 * See file CREDITS for list of people who contributed to this
31 * Modified for DV-EVM board by Swaminathan S, Nov 2005
32 * See file CREDITS for list of people who contributed to this
35 * This program is free software; you can redistribute it and/or
36 * modify it under the terms of the GNU General Public License as
37 * published by the Free Software Foundation; either version 2 of
38 * the License, or (at your option) any later version.
40 * This program is distributed in the hope that it will be useful,
41 * but WITHOUT ANY WARRANTY; without even the implied warranty of
42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 * GNU General Public License for more details.
45 * You should have received a copy of the GNU General Public License
46 * along with this program; if not, write to the Free Software
47 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
56 /*-------------------------------------------------------*
57 * Mask all IRQs by setting all bits in the EINT default *
58 *-------------------------------------------------------*/
65 /*------------------------------------------------------*
66 * Put the GEM in reset *
67 *------------------------------------------------------*/
69 /* Put the GEM in reset */
70 ldr r8, PSC_GEM_FLAG_CLEAR
76 /* Enable the Power Domain Transition Command */
82 /* Check for Transition Complete(PTSTAT) */
87 bne checkStatClkStopGem
89 /* Check for GEM Reset Completion */
94 bne checkGemStatClkStop
96 /* Do this for enabling a WDT initiated reset this is a workaround
97 for a chip bug. Not required under normal situations */
102 /*------------------------------------------------------*
103 * Enable L1 & L2 Memories in Fast mode *
104 *------------------------------------------------------*/
110 ldr r10, MMARG_BRF0_VAL
117 /*------------------------------------------------------*
118 * DDR2 PLL Initialization *
119 *------------------------------------------------------*/
121 /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
124 ldr r7, PLL_CLKSRC_MASK
131 /* Select the PLLEN source */
132 ldr r7, PLL_ENSRC_MASK
137 ldr r7, PLL_BYPASS_MASK
141 /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
148 ldr r7, PLL_RESET_MASK
152 /* Power up the PLL */
153 ldr r7, PLL_PWRUP_MASK
157 /* Enable the PLL from Disable Mode */
158 ldr r7, PLL_DISABLE_ENABLE_MASK
162 /* Program the PLL Multiplier */
164 mov r2, $CFG_DAVINCI_PLL2_PLLM
167 /* Program the PLL2 Divisor Value */
169 mov r3, $CFG_DAVINCI_PLL2_DIV2
172 /* Program the PLL2 Divisor Value */
174 mov r4, $CFG_DAVINCI_PLL2_DIV1
178 ldr r8, PLL2_DIV_MASK
187 /* Program the GOSET bit to take new divider values */
201 ldr r8, PLL2_DIV_MASK
210 /* Program the GOSET bit to take new divider values */
223 /* Wait for PLL to Reset Properly */
229 /* Bring PLL out of Reset */
235 /* Wait for PLL to Lock */
236 ldr r10, PLL_LOCK_COUNT
247 /*------------------------------------------------------*
248 * Issue Soft Reset to DDR Module *
249 *------------------------------------------------------*/
251 /* Shut down the DDR2 LPSC Module */
252 ldr r8, PSC_FLAG_CLEAR
259 /* Enable the Power Domain Transition Command */
265 /* Check for Transition Complete(PTSTAT) */
272 /* Check for DDR2 Controller Enable Completion */
278 bne checkDDRStatClkStop
280 /*------------------------------------------------------*
281 * Program DDR2 MMRs *
282 *------------------------------------------------------*/
284 /* Program PHY Control Register */
289 /* Program SDRAM Bank Config Register */
294 /* Program SDRAM TIM-0 Config Register */
299 /* Program SDRAM TIM-1 Config Register */
304 /* Program the SDRAM Bank Config Control Register */
311 /* Program SDRAM SDREF Config Register */
316 /*------------------------------------------------------*
317 * Issue Soft Reset to DDR Module *
318 *------------------------------------------------------*/
320 /* Issue a Dummy DDR2 read/write */
321 ldr r8, DDR2_START_ADDR
326 /* Shut down the DDR2 LPSC Module */
327 ldr r8, PSC_FLAG_CLEAR
334 /* Enable the Power Domain Transition Command */
340 /* Check for Transition Complete(PTSTAT) */
345 bne checkStatClkStop2
347 /* Check for DDR2 Controller Enable Completion */
348 checkDDRStatClkStop2:
353 bne checkDDRStatClkStop2
355 /*------------------------------------------------------*
356 * Turn DDR2 Controller Clocks On *
357 *------------------------------------------------------*/
359 /* Enable the DDR2 LPSC Module */
365 /* Enable the Power Domain Transition Command */
371 /* Check for Transition Complete(PTSTAT) */
378 /* Check for DDR2 Controller Enable Completion */
384 bne checkDDRStatClkEn2
386 /* DDR Writes and Reads */
391 /*------------------------------------------------------*
392 * System PLL Initialization *
393 *------------------------------------------------------*/
395 /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
398 ldr r7, PLL_CLKSRC_MASK
405 /* Select the PLLEN source */
406 ldr r7, PLL_ENSRC_MASK
411 ldr r7, PLL_BYPASS_MASK
415 /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
423 ldr r7, PLL_RESET_MASK
427 /* Disable the PLL */
431 /* Power up the PLL */
432 ldr r7, PLL_PWRUP_MASK
436 /* Enable the PLL from Disable Mode */
437 ldr r7, PLL_DISABLE_ENABLE_MASK
441 /* Program the PLL Multiplier */
443 mov r3, $CFG_DAVINCI_PLL1_PLLM
446 /* Wait for PLL to Reset Properly */
453 /* Bring PLL out of Reset */
458 /* Wait for PLL to Lock */
459 ldr r10, PLL_LOCK_COUNT
474 /*------------------------------------------------------*
475 * AEMIF configuration for NAND/NOR Flash *
476 *------------------------------------------------------*/
517 /*--------------------------------------*
518 * VTP manual Calibration *
519 *--------------------------------------*/
528 /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
529 ldr r10, VTP_LOCK_COUNT
550 /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
551 ldr r10, VTP_LOCK_COUNT
566 * Call board-specific lowlevel init.
567 * That MUST be present and THAT returns
568 * back to arch calling code with "mov pc, lr."
575 .word 0x01c40000 /* Device Configuration Registers */
577 .word 0x01c40004 /* Device Configuration Registers */
580 .word CFG_DAVINCI_PINMUX_0
585 .word CFG_DAVINCI_WAITCFG
589 .word CFG_DAVINCI_ACFG2
593 .word CFG_DAVINCI_ACFG3
597 .word CFG_DAVINCI_ACFG4
601 .word CFG_DAVINCI_ACFG5
605 #ifdef CFG_DAVINCI_NANDCE
606 .word (1 << (CFG_DAVINCI_NANDCE - 2))
631 /* DDR2 MMR & CONFIGURATION VALUES */
635 .word CFG_DAVINCI_DDRCTL
639 .word CFG_DAVINCI_SDREF
643 .word CFG_DAVINCI_SDCFG
647 .word CFG_DAVINCI_SDTIM0
651 .word CFG_DAVINCI_SDTIM1
653 .word 0x200000f0 /* VTP IO Control register */
655 .word 0x01c42030 /* DDR VPTR MMR */
675 /* GEM Power Up & LPSC Control Register */
681 /* For WDT reset chip bug */
686 .word 0xfffffeff /* Mask the Clock Mode bit */
688 .word 0xffffffdf /* Select the PLLEN source */
690 .word 0xfffffffe /* Put the PLL in BYPASS */
692 .word 0xfffffff7 /* Put the PLL in Reset Mode */
694 .word 0xfffffffd /* PLL Power up Mask Bit */
695 PLL_DISABLE_ENABLE_MASK:
696 .word 0xffffffef /* Enable the PLL from Disable */
700 /* PLL1-SYSTEM PLL MMRs */
706 /* PLL2-SYSTEM PLL MMRs */
723 .word 0x01c42010 /* BRF margin mode 0 (R/W)*/
725 .word CFG_DAVINCI_MMARG_BRF0