2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
8 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/hardware.h>
32 #include <asm/arch/at91_pmc.h>
33 #include <asm/arch/at91_pio.h>
34 #include <asm/arch/at91_rstc.h>
35 #include <asm/arch/at91_wdt.h>
36 #include <asm/arch/at91sam9_matrix.h>
37 #include <asm/arch/at91sam9_sdramc.h>
38 #include <asm/arch/at91sam9_smc.h>
44 .type lowlevel_init,function
47 mov r5, pc /* r5 = POS1 + 4 current */
49 ldr r0, =POS1 /* r0 = POS1 compile */
51 sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
52 sub r5, r5, r0 /* r0 = TEXT_BASE-1 */
53 sub r5, r5, #4 /* r1 = text base - current */
55 /* memory control configuration 1 */
72 /* ----------------------------------------------------------------------------
74 * ----------------------------------------------------------------------------
75 * - Check if the PLL is already initialized
76 * ----------------------------------------------------------------------------
78 ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
84 /* ---------------------------------------------------------------------------
85 * - Enable the Main Oscillator
86 * ---------------------------------------------------------------------------
88 ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
89 ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
90 /* Main oscillator Enable register PMC_MOR: */
91 ldr r0, =CONFIG_SYS_MOR_VAL
94 /* Reading the PMC Status to detect when the Main Oscillator is enabled */
95 mov r4, #AT91_PMC_MOSCS
99 cmp r3, #AT91_PMC_MOSCS
102 /* ----------------------------------------------------------------------------
104 * ----------------------------------------------------------------------------
106 * ----------------------------------------------------------------------------
108 ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
109 ldr r0, =CONFIG_SYS_PLLAR_VAL
112 /* Reading the PMC Status register to detect when the PLLA is locked */
113 mov r4, #AT91_PMC_LOCKA
117 cmp r3, #AT91_PMC_LOCKA
120 /* ----------------------------------------------------------------------------
122 * ----------------------------------------------------------------------------
123 * - Switch on the Main Oscillator
124 * ----------------------------------------------------------------------------
126 ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
128 /* -Master Clock Controller register PMC_MCKR */
129 ldr r0, =CONFIG_SYS_MCKR1_VAL
132 /* Reading the PMC Status to detect when the Master clock is ready */
133 mov r4, #AT91_PMC_MCKRDY
137 cmp r3, #AT91_PMC_MCKRDY
140 ldr r0, =CONFIG_SYS_MCKR2_VAL
143 /* Reading the PMC Status to detect when the Master clock is ready */
144 mov r4, #AT91_PMC_MCKRDY
148 cmp r3, #AT91_PMC_MCKRDY
153 /* ----------------------------------------------------------------------------
154 * - memory control configuration 2
155 * ----------------------------------------------------------------------------
157 ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
180 /* everything is fine now */
186 .word (AT91_BASE_SYS + AT91_WDT_MR)
187 .word CONFIG_SYS_WDTC_WDMR_VAL
189 /* configure PIOx as EBI0 D[16-31] */
190 #if defined(CONFIG_AT91SAM9263)
191 .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
192 .word CONFIG_SYS_PIOD_PDR_VAL1
193 .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
194 .word CONFIG_SYS_PIOD_PPUDR_VAL
195 .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
196 .word CONFIG_SYS_PIOD_PPUDR_VAL
197 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
198 || defined(CONFIG_AT91SAM9G20)
199 .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
200 .word CONFIG_SYS_PIOC_PDR_VAL1
201 .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)
202 .word CONFIG_SYS_PIOC_PPUDR_VAL
205 #if defined(AT91_MATRIX_EBI0CSA)
206 .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
207 .word CONFIG_SYS_MATRIX_EBI0CSA_VAL
208 #else /* AT91_MATRIX_EBICSA */
209 .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA)
210 .word CONFIG_SYS_MATRIX_EBICSA_VAL
214 .word (AT91_BASE_SYS + AT91_SMC_MODE(0))
215 .word CONFIG_SYS_SMC0_MODE0_VAL
217 .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
218 .word CONFIG_SYS_SMC0_CYCLE0_VAL
220 .word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
221 .word CONFIG_SYS_SMC0_PULSE0_VAL
223 .word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
224 .word CONFIG_SYS_SMC0_SETUP0_VAL
227 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
228 .word CONFIG_SYS_SDRC_MR_VAL1
229 .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
230 .word CONFIG_SYS_SDRC_TR_VAL1
231 .word (AT91_BASE_SYS + AT91_SDRAMC_CR)
232 .word CONFIG_SYS_SDRC_CR_VAL
233 .word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
234 .word CONFIG_SYS_SDRC_MDR_VAL
235 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
236 .word CONFIG_SYS_SDRC_MR_VAL2
237 .word AT91_SDRAM_BASE
238 .word CONFIG_SYS_SDRAM_VAL1
239 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
240 .word CONFIG_SYS_SDRC_MR_VAL3
241 .word AT91_SDRAM_BASE
242 .word CONFIG_SYS_SDRAM_VAL2
243 .word AT91_SDRAM_BASE
244 .word CONFIG_SYS_SDRAM_VAL3
245 .word AT91_SDRAM_BASE
246 .word CONFIG_SYS_SDRAM_VAL4
247 .word AT91_SDRAM_BASE
248 .word CONFIG_SYS_SDRAM_VAL5
249 .word AT91_SDRAM_BASE
250 .word CONFIG_SYS_SDRAM_VAL6
251 .word AT91_SDRAM_BASE
252 .word CONFIG_SYS_SDRAM_VAL7
253 .word AT91_SDRAM_BASE
254 .word CONFIG_SYS_SDRAM_VAL8
255 .word AT91_SDRAM_BASE
256 .word CONFIG_SYS_SDRAM_VAL9
257 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
258 .word CONFIG_SYS_SDRC_MR_VAL4
259 .word AT91_SDRAM_BASE
260 .word CONFIG_SYS_SDRAM_VAL10
261 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
262 .word CONFIG_SYS_SDRC_MR_VAL5
263 .word AT91_SDRAM_BASE
264 .word CONFIG_SYS_SDRAM_VAL11
265 .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
266 .word CONFIG_SYS_SDRC_TR_VAL2
267 .word AT91_SDRAM_BASE
268 .word CONFIG_SYS_SDRAM_VAL12
269 /* User reset enable*/
270 .word (AT91_BASE_SYS + AT91_RSTC_MR)
271 .word CONFIG_SYS_RSTC_RMR_VAL
272 #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
273 /* MATRIX_MCFG - REMAP all masters */
274 .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)