2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from RAM!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
82 * These are defined in the board-specific linker script.
93 /* IRQ stack memory (calculated at run-time) */
94 .globl IRQ_STACK_START
98 /* IRQ stack memory (calculated at run-time) */
99 .globl FIQ_STACK_START
106 * the actual reset code
111 * set the cpu to SVC32 mode
119 * we do sys-critical inits only at reboot,
120 * not when booting from ram!
122 #ifdef CONFIG_INIT_CRITICAL
126 relocate: /* relocate U-Boot to RAM */
127 adr r0, _start /* r0 <- current position of code */
128 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
129 cmp r0, r1 /* don't reloc during debug */
132 ldr r2, _armboot_start
134 sub r2, r3, r2 /* r2 <- size of armboot */
135 add r2, r0, r2 /* r2 <- source end address */
138 ldmia r0!, {r3-r10} /* copy from source address [r0] */
139 stmia r1!, {r3-r10} /* copy to target address [r1] */
140 cmp r0, r2 /* until source end addreee [r2] */
143 /* Set up the stack */
145 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
146 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
147 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
148 #ifdef CONFIG_USE_IRQ
149 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
151 sub sp, r0, #12 /* leave 3 words for abort-stack */
154 ldr r0, _bss_start /* find start of bss segment */
155 add r0, r0, #4 /* start at first byte of bss */
156 ldr r1, _bss_end /* stop here */
157 mov r2, #0x00000000 /* clear */
159 clbss_l:str r2, [r0] /* clear loop... */
164 ldr pc, _start_armboot
166 _start_armboot: .word start_armboot
170 *************************************************************************
172 * CPU_init_critical registers
174 * setup important registers
175 * setup memory timing
177 *************************************************************************
181 /* Interupt-Controller base addresses */
182 INTMR1: .word 0x80000280 @ 32 bit size
183 INTMR2: .word 0x80001280 @ 16 bit size
184 INTMR3: .word 0x80002280 @ 8 bit size
187 SYSCON1: .word 0x80000100
188 SYSCON2: .word 0x80001100
189 SYSCON3: .word 0x80002200
191 #define CLKCTL 0x6 /* mask */
192 #define CLKCTL_18 0x0 /* 18.432 MHz */
193 #define CLKCTL_36 0x2 /* 36.864 MHz */
194 #define CLKCTL_49 0x4 /* 49.152 MHz */
195 #define CLKCTL_73 0x6 /* 73.728 MHz */
199 * mask all IRQs by clearing all bits in the INTMRs
210 * flush v4 I/D caches
213 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
214 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
217 * disable MMU stuff and caches
220 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
221 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
222 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
225 #ifdef CONFIG_ARM7_REVD
226 /* set clock speed */
227 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
228 /* !!! not doing DRAM refresh properly! */
232 orr r1, r1, #CLKCTL_36
237 * before relocating, we have to setup RAM timing
238 * because memory timing is board-dependent, you will
239 * find a memsetup.S in your board directory.
249 *************************************************************************
253 *************************************************************************
259 #define S_FRAME_SIZE 72
281 #define MODE_SVC 0x13
285 * use bad_save_user_regs for abort/prefetch/undef/swi ...
286 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
289 .macro bad_save_user_regs
290 sub sp, sp, #S_FRAME_SIZE
291 stmia sp, {r0 - r12} @ Calling r0-r12
294 ldr r2, _armboot_start
295 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
296 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
297 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
298 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
302 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
306 .macro irq_save_user_regs
307 sub sp, sp, #S_FRAME_SIZE
308 stmia sp, {r0 - r12} @ Calling r0-r12
310 stmdb r8, {sp, lr}^ @ Calling SP, LR
311 str lr, [r8, #0] @ Save calling PC
313 str r6, [r8, #4] @ Save CPSR
314 str r0, [r8, #8] @ Save OLD_R0
318 .macro irq_restore_user_regs
319 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
321 ldr lr, [sp, #S_PC] @ Get PC
322 add sp, sp, #S_FRAME_SIZE
323 subs pc, lr, #4 @ return & move spsr_svc into cpsr
327 ldr r13, _armboot_start @ setup our mode stack
328 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
329 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
331 str lr, [r13] @ save caller lr / spsr
335 mov r13, #MODE_SVC @ prepare SVC-Mode
341 .macro get_irq_stack @ setup IRQ stack
342 ldr sp, IRQ_STACK_START
345 .macro get_fiq_stack @ setup FIQ stack
346 ldr sp, FIQ_STACK_START
353 undefined_instruction:
356 bl do_undefined_instruction
362 bl do_software_interrupt
382 #ifdef CONFIG_USE_IRQ
389 irq_restore_user_regs
394 /* someone ought to write a more effiction fiq_save_user_regs */
397 irq_restore_user_regs
419 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
420 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
421 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
422 bic ip, ip, #0x000f @ ............wcam
423 bic ip, ip, #0x2100 @ ..v....s........
424 mcr p15, 0, ip, c1, c0, 0 @ ctrl register