2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/hardware.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from RAM!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
82 * These are defined in the board-specific linker script.
93 /* IRQ stack memory (calculated at run-time) */
94 .globl IRQ_STACK_START
98 /* IRQ stack memory (calculated at run-time) */
99 .globl FIQ_STACK_START
106 * the actual reset code
111 * set the cpu to SVC32 mode
119 * we do sys-critical inits only at reboot,
120 * not when booting from ram!
122 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
126 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
127 relocate: /* relocate U-Boot to RAM */
128 adr r0, _start /* r0 <- current position of code */
129 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
130 cmp r0, r1 /* don't reloc during debug */
134 ldr r2, =0x0 /* Relocate the exception vectors */
135 cmp r1, r2 /* and associated data to address */
136 ldmneia r0!, {r3-r10} /* 0x0. Do nothing if TEXT_BASE is */
137 stmneia r2!, {r3-r10} /* 0x0. Copy the first 15 words. */
140 adrne r0, _start /* restore r0 */
143 ldr r2, _armboot_start
145 sub r2, r3, r2 /* r2 <- size of armboot */
146 add r2, r0, r2 /* r2 <- source end address */
149 ldmia r0!, {r3-r10} /* copy from source address [r0] */
150 stmia r1!, {r3-r10} /* copy to target address [r1] */
151 cmp r0, r2 /* until source end addreee [r2] */
154 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
156 /* Set up the stack */
158 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
159 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
160 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
161 #ifdef CONFIG_USE_IRQ
162 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
164 sub sp, r0, #12 /* leave 3 words for abort-stack */
167 ldr r0, _bss_start /* find start of bss segment */
168 ldr r1, _bss_end /* stop here */
169 mov r2, #0x00000000 /* clear */
171 clbss_l:str r2, [r0] /* clear loop... */
176 ldr pc, _start_armboot
178 _start_armboot: .word start_armboot
181 *************************************************************************
183 * CPU_init_critical registers
185 * setup important registers
186 * setup memory timing
188 *************************************************************************
191 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
193 /* Interupt-Controller base addresses */
194 INTMR1: .word 0x80000280 @ 32 bit size
195 INTMR2: .word 0x80001280 @ 16 bit size
196 INTMR3: .word 0x80002280 @ 8 bit size
199 SYSCON1: .word 0x80000100
200 SYSCON2: .word 0x80001100
201 SYSCON3: .word 0x80002200
203 #define CLKCTL 0x6 /* mask */
204 #define CLKCTL_18 0x0 /* 18.432 MHz */
205 #define CLKCTL_36 0x2 /* 36.864 MHz */
206 #define CLKCTL_49 0x4 /* 49.152 MHz */
207 #define CLKCTL_73 0x6 /* 73.728 MHz */
212 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
215 * mask all IRQs by clearing all bits in the INTMRs
226 * flush v4 I/D caches
229 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
230 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
233 * disable MMU stuff and caches
236 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
237 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
238 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
240 #elif defined(CONFIG_NETARM)
242 * prior to software reset : need to set pin PORTC4 to be *HRESET
244 ldr r0, =NETARM_GEN_MODULE_BASE
245 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
246 NETARM_GEN_PORT_DIR(0x10))
247 str r1, [r0, #+NETARM_GEN_PORTC]
249 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
250 * for an explanation of this process
252 ldr r0, =NETARM_GEN_MODULE_BASE
253 ldr r1, =NETARM_GEN_SW_SVC_RESETA
254 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
255 ldr r1, =NETARM_GEN_SW_SVC_RESETB
256 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
257 ldr r1, =NETARM_GEN_SW_SVC_RESETA
258 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
259 ldr r1, =NETARM_GEN_SW_SVC_RESETB
260 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
262 * setup PLL and System Config
264 ldr r0, =NETARM_GEN_MODULE_BASE
266 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
267 NETARM_GEN_SYS_CFG_BUSFULL | \
268 NETARM_GEN_SYS_CFG_USER_EN | \
269 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
270 NETARM_GEN_SYS_CFG_BUSARB_INT | \
271 NETARM_GEN_SYS_CFG_BUSMON_EN )
273 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
275 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
276 NETARM_GEN_PLL_CTL_POLTST_DEF | \
277 NETARM_GEN_PLL_CTL_INDIV(1) | \
278 NETARM_GEN_PLL_CTL_ICP_DEF | \
279 NETARM_GEN_PLL_CTL_OUTDIV(2) )
280 str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
282 * mask all IRQs by clearing all bits in the INTMRs
285 ldr r0, =NETARM_GEN_MODULE_BASE
286 str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
288 #elif defined(CONFIG_S3C4510B)
291 * Mask off all IRQ sources
301 ldr r1, =0x83ffffa0 /* cache-disabled */
305 #error No cpu_init_crit() defined for current CPU type
308 #ifdef CONFIG_ARM7_REVD
309 /* set clock speed */
310 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
311 /* !!! not doing DRAM refresh properly! */
315 orr r1, r1, #CLKCTL_36
320 * before relocating, we have to setup RAM timing
321 * because memory timing is board-dependent, you will
322 * find a lowlevel_init.S in your board directory.
332 *************************************************************************
336 *************************************************************************
342 #define S_FRAME_SIZE 72
364 #define MODE_SVC 0x13
368 * use bad_save_user_regs for abort/prefetch/undef/swi ...
369 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
372 .macro bad_save_user_regs
373 sub sp, sp, #S_FRAME_SIZE
374 stmia sp, {r0 - r12} @ Calling r0-r12
377 ldr r2, _armboot_start
378 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
379 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
380 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
381 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
385 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
389 .macro irq_save_user_regs
390 sub sp, sp, #S_FRAME_SIZE
391 stmia sp, {r0 - r12} @ Calling r0-r12
393 stmdb r8, {sp, lr}^ @ Calling SP, LR
394 str lr, [r8, #0] @ Save calling PC
396 str r6, [r8, #4] @ Save CPSR
397 str r0, [r8, #8] @ Save OLD_R0
401 .macro irq_restore_user_regs
402 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
404 ldr lr, [sp, #S_PC] @ Get PC
405 add sp, sp, #S_FRAME_SIZE
406 subs pc, lr, #4 @ return & move spsr_svc into cpsr
410 ldr r13, _armboot_start @ setup our mode stack
411 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
412 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
414 str lr, [r13] @ save caller lr / spsr
418 mov r13, #MODE_SVC @ prepare SVC-Mode
424 .macro get_irq_stack @ setup IRQ stack
425 ldr sp, IRQ_STACK_START
428 .macro get_fiq_stack @ setup FIQ stack
429 ldr sp, FIQ_STACK_START
436 undefined_instruction:
439 bl do_undefined_instruction
445 bl do_software_interrupt
465 #ifdef CONFIG_USE_IRQ
472 irq_restore_user_regs
477 /* someone ought to write a more effiction fiq_save_user_regs */
480 irq_restore_user_regs
498 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
503 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
504 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
505 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
506 bic ip, ip, #0x000f @ ............wcam
507 bic ip, ip, #0x2100 @ ..v....s........
508 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
510 #elif defined(CONFIG_NETARM)
514 ldr r1, =NETARM_MEM_MODULE_BASE
515 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
518 ldr r1, =(relocate-TEXT_BASE)
520 ldr r4, =NETARM_GEN_MODULE_BASE
521 ldr r1, =NETARM_GEN_SW_SVC_RESETA
522 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
523 ldr r1, =NETARM_GEN_SW_SVC_RESETB
524 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
525 ldr r1, =NETARM_GEN_SW_SVC_RESETA
526 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
527 ldr r1, =NETARM_GEN_SW_SVC_RESETB
528 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
530 #elif defined(CONFIG_S3C4510B)
531 /* Nothing done here as reseting the CPU is board specific, depending
532 * on external peripherals such as watchdog timers, etc. */
534 #error No reset_cpu() defined for current CPU type