2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
75 * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
85 * Note: _armboot_end_data and _armboot_end are defined
86 * by the (board-dependent) linker script.
87 * _armboot_end_data is the first usable FLASH address after armboot
89 .globl _armboot_end_data
91 .word armboot_end_data
97 * _armboot_real_end is the first usable RAM address behind armboot
98 * and the various stacks
100 .globl _armboot_real_end
104 #ifdef CONFIG_USE_IRQ
105 /* IRQ stack memory (calculated at run-time) */
106 .globl IRQ_STACK_START
110 /* IRQ stack memory (calculated at run-time) */
111 .globl FIQ_STACK_START
118 * the actual reset code
123 * set the cpu to SVC32 mode
131 * we do sys-critical inits only at reboot,
132 * not when booting from ram!
134 #ifdef CONFIG_INIT_CRITICAL
140 * relocate armboot to RAM
142 adr r0, _start /* r0 <- current position of code */
143 ldr r2, _armboot_start
145 sub r2, r3, r2 /* r2 <- size of armboot */
146 ldr r1, _TEXT_BASE /* r1 <- destination address */
147 add r2, r0, r2 /* r2 <- source end address */
150 * r0 = source address
151 * r1 = target address
152 * r2 = source end address
160 /* set up the stack */
162 add r0, r0, #CONFIG_STACKSIZE
163 sub sp, r0, #12 /* leave 3 words for abort-stack */
165 ldr pc, _start_armboot
167 _start_armboot: .word start_armboot
171 *************************************************************************
173 * CPU_init_critical registers
175 * setup important registers
176 * setup memory timing
178 *************************************************************************
182 /* Interupt-Controller base addresses */
183 INTMR1: .word 0x80000280 @ 32 bit size
184 INTMR2: .word 0x80001280 @ 16 bit size
185 INTMR3: .word 0x80002280 @ 8 bit size
188 SYSCON1: .word 0x80000100
189 SYSCON2: .word 0x80001100
190 SYSCON3: .word 0x80002200
192 #define CLKCTL 0x6 /* mask */
193 #define CLKCTL_18 0x0 /* 18.432 MHz */
194 #define CLKCTL_36 0x2 /* 36.864 MHz */
195 #define CLKCTL_49 0x4 /* 49.152 MHz */
196 #define CLKCTL_73 0x6 /* 73.728 MHz */
200 * mask all IRQs by clearing all bits in the INTMRs
211 * flush v4 I/D caches
214 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
215 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
218 * disable MMU stuff and caches
221 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
222 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
223 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
226 #ifdef CONFIG_ARM7_REVD
227 /* set clock speed */
228 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
229 /* !!! not doing DRAM refresh properly! */
233 orr r1, r1, #CLKCTL_36
238 * before relocating, we have to setup RAM timing
239 * because memory timing is board-dependend, you will
240 * find a memsetup.S in your board directory.
250 *************************************************************************
254 *************************************************************************
260 #define S_FRAME_SIZE 72
282 #define MODE_SVC 0x13
286 * use bad_save_user_regs for abort/prefetch/undef/swi ...
287 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
290 .macro bad_save_user_regs
291 sub sp, sp, #S_FRAME_SIZE
292 stmia sp, {r0 - r12} @ Calling r0-r12
296 add r2, r2, #CONFIG_STACKSIZE
298 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
299 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
303 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
307 .macro irq_save_user_regs
308 sub sp, sp, #S_FRAME_SIZE
309 stmia sp, {r0 - r12} @ Calling r0-r12
311 stmdb r8, {sp, lr}^ @ Calling SP, LR
312 str lr, [r8, #0] @ Save calling PC
314 str r6, [r8, #4] @ Save CPSR
315 str r0, [r8, #8] @ Save OLD_R0
319 .macro irq_restore_user_regs
320 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
322 ldr lr, [sp, #S_PC] @ Get PC
323 add sp, sp, #S_FRAME_SIZE
324 subs pc, lr, #4 @ return & move spsr_svc into cpsr
328 ldr r13, _armboot_end @ setup our mode stack
329 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
332 str lr, [r13] @ save caller lr / spsr
336 mov r13, #MODE_SVC @ prepare SVC-Mode
342 .macro get_irq_stack @ setup IRQ stack
343 ldr sp, IRQ_STACK_START
346 .macro get_fiq_stack @ setup FIQ stack
347 ldr sp, FIQ_STACK_START
354 undefined_instruction:
357 bl do_undefined_instruction
363 bl do_software_interrupt
383 #ifdef CONFIG_USE_IRQ
390 irq_restore_user_regs
395 /* someone ought to write a more effiction fiq_save_user_regs */
398 irq_restore_user_regs
420 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
421 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
422 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
423 bic ip, ip, #0x000f @ ............wcam
424 bic ip, ip, #0x2100 @ ..v....s........
425 mcr p15, 0, ip, c1, c0, 0 @ ctrl register