2 * Copyright (c) 2014, Allwinner Technology Co., Ltd.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
27 #include <platform_config.h>
29 #include <drivers/sunxi_uart.h>
33 /* uart register defines */
34 #define UART_REG_RBR (0x00)
35 #define UART_REG_THR (0x00)
36 #define UART_REG_DLL (0x00)
37 #define UART_REG_DLH (0x04)
38 #define UART_REG_IER (0x04)
39 #define UART_REG_IIR (0x08)
40 #define UART_REG_FCR (0x08)
41 #define UART_REG_LCR (0x0c)
42 #define UART_REG_MCR (0x10)
43 #define UART_REG_LSR (0x14)
44 #define UART_REG_MSR (0x18)
45 #define UART_REG_SCH (0x1c)
46 #define UART_REG_USR (0x7c)
47 #define UART_REG_TFL (0x80)
48 #define UART_REG_RFL (0x84)
49 #define UART_REG_HALT (0xa4)
51 /* uart status register bits */
52 #define UART_REG_USR_BUSY (0x1 << 0x0)
53 #define UART_REG_USR_TFNF (0x1 << 0x1)
54 #define UART_REG_USR_TFE (0x1 << 0x2)
55 #define UART_REG_USR_RFNE (0x1 << 0x3)
56 #define UART_REG_USR_RFF (0x1 << 0x4)
58 void sunxi_uart_init(vaddr_t __unused base)
60 /* do nothing, debug uart(uart0) share with normal world,
61 * everything for uart0 is ready now.
65 void sunxi_uart_flush(vaddr_t base)
67 while (read32(base + UART_REG_TFL)) {
68 /* waiting transmit fifo empty */
73 bool sunxi_uart_have_rx_data(vaddr_t base)
75 return read32(base + UART_REG_RFL);
78 void sunxi_uart_putc(int ch, vaddr_t base)
80 while (!(read32(base + UART_REG_USR) & UART_REG_USR_TFNF)) {
81 /* transmit fifo is full, waiting again. */
85 /* write out charset to transmit fifo */
86 write8(ch, base + UART_REG_THR);
89 int sunxi_uart_getchar(vaddr_t base)
91 while (!sunxi_uart_have_rx_data(base)) {
92 /* transmit fifo is empty, waiting again. */
95 return read32(base + UART_REG_RBR) & 0xff;