2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
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12 * this list of conditions and the following disclaimer in the documentation
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15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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28 #include <platform_config.h>
30 #include <drivers/imx_uart.h>
35 /* Register definitions */
36 #define URXD 0x0 /* Receiver Register */
37 #define UTXD 0x40 /* Transmitter Register */
38 #define UCR1 0x80 /* Control Register 1 */
39 #define UCR2 0x84 /* Control Register 2 */
40 #define UCR3 0x88 /* Control Register 3 */
41 #define UCR4 0x8c /* Control Register 4 */
42 #define UFCR 0x90 /* FIFO Control Register */
43 #define USR1 0x94 /* Status Register 1 */
44 #define USR2 0x98 /* Status Register 2 */
45 #define UESC 0x9c /* Escape Character Register */
46 #define UTIM 0xa0 /* Escape Timer Register */
47 #define UBIR 0xa4 /* BRM Incremental Register */
48 #define UBMR 0xa8 /* BRM Modulator Register */
49 #define UBRC 0xac /* Baud Rate Count Register */
50 #define UTS 0xb4 /* UART Test Register (mx31) */
52 /* UART Control Register Bit Fields.*/
53 #define URXD_CHARRDY (1<<15)
54 #define URXD_ERR (1<<14)
55 #define URXD_OVRRUN (1<<13)
56 #define URXD_FRMERR (1<<12)
57 #define URXD_BRK (1<<11)
58 #define URXD_PRERR (1<<10)
59 #define URXD_RX_DATA (0xFF)
60 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
61 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
62 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
63 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
64 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
65 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
66 #define UCR1_IREN (1<<7) /* Infrared interface enable */
67 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
68 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
69 #define UCR1_SNDBRK (1<<4) /* Send break */
70 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
71 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
72 #define UCR1_DOZE (1<<1) /* Doze */
73 #define UCR1_UARTEN (1<<0) /* UART enabled */
75 #define UTS_FRCPERR (1<<13) /* Force parity error */
76 #define UTS_LOOP (1<<12) /* Loop tx and rx */
77 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
78 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
79 #define UTS_TXFULL (1<<4) /* TxFIFO full */
80 #define UTS_RXFULL (1<<3) /* RxFIFO full */
81 #define UTS_SOFTRST (1<<0) /* Software reset */
83 void imx_uart_init(vaddr_t __unused vbase)
86 * Do nothing, debug uart(uart0) share with normal world,
87 * everything for uart0 intialization is done in bootloader.
91 void imx_uart_flush_tx_fifo(vaddr_t base)
93 while (!(read32(base + UTS) & UTS_TXEMPTY))
97 int imx_uart_getchar(vaddr_t base)
99 while (read32(base + UTS) & UTS_RXEMPTY)
102 return (read32(base + URXD) & URXD_RX_DATA);
105 void imx_uart_putc(const char c, vaddr_t base)
107 write32(c, base + UTXD);
109 /* wait until sent */
110 while (!(read32(base + UTS) & UTS_TXEMPTY))