2 * Copyright (c) 2016, Linaro Limited
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
27 #include <drivers/hi16xx_uart.h>
30 /* Register offsets */
32 #define UART_RBR 0x00 /* RX data buffer register */
33 #define UART_THR 0x00 /* TX data buffer register */
34 #define UART_DLL 0x00 /* Lower-bit frequency divider register */
36 #define UART_IEL 0x04 /* Interrupt enable register */
37 #define UART_DLH 0x04 /* Upper-bit frequency divider register */
39 #define UART_FCR 0x08 /* FIFO control register */
41 #define UART_LCR 0x0C /* Line control register */
43 #define UART_LSR 0x14 /* Line status register */
45 #define UART_USR 0x7C /* Status register */
48 * Line control register
51 /* Data length selection */
52 #define UART_LCR_DLS5 0x0 /* 5 bits */
53 #define UART_LCR_DLS6 0x1 /* 6 bits */
54 #define UART_LCR_DLS7 0x2 /* 7 bits */
55 #define UART_LCR_DLS8 0x3 /* 8 bits */
57 /* Enable access to UART_DLL and UART_DLH */
58 #define UART_LCR_DLAB 0x80
61 * FIFO control register
64 #define UART_FCR_FIFO_EN 0x1 /* Enable FIFO (depth: 32 bytes) */
65 #define UART_FCR_RX_FIFO_RST 0x2 /* Clear receive FIFO (auto reset) */
66 #define UART_FCR_TX_FIFO_RST 0x4 /* Clear send FIFO (auto reset) */
73 #define UART_USR_BUSY_BIT 0 /* 0: idle/non-activated, 1: busy */
74 #define UART_USR_TFNF_BIT 1 /* Transmit FIFO not full bit */
75 #define UART_USR_TFE_BIT 2 /* Transmit FIFO empty bit */
76 #define UART_USR_RFNE_BIT 3 /* Receive FIFO not empty bit */
77 #define UART_USR_RFF_BIT 4 /* Receive FIFO full bit */
79 void hi16xx_uart_flush(vaddr_t base)
81 while (!(read32(base + UART_USR) & UART_USR_TFE_BIT))
85 void hi16xx_uart_init(vaddr_t base, uint32_t uart_clk, uint32_t baud_rate)
87 uint16_t freq_div = uart_clk / (16 * baud_rate);
89 /* Enable (and clear) FIFOs */
90 write32(UART_FCR_FIFO_EN, base + UART_FCR);
92 /* Enable access to _DLL and _DLH */
93 write32(UART_LCR_DLAB, base + UART_LCR);
95 /* Calculate and set UART_DLL */
96 write32(freq_div & 0xFF, base + UART_DLL);
98 /* Calculate and set UART_DLH */
99 write32((freq_div >> 8) & 0xFF, base + UART_DLH);
101 /* Clear _DLL/_DLH access bit, set data size (8 bits), parity etc. */
102 write32(UART_LCR_DLS8, base + UART_LCR);
104 /* Disable interrupt mode */
105 write32(0, base + UART_IEL);
107 hi16xx_uart_flush(base);
110 void hi16xx_uart_putc(int ch, vaddr_t base)
112 /* Wait until TX FIFO is empty */
113 while (!(read32(base + UART_USR) & UART_USR_TFE_BIT))
116 /* Put character into TX FIFO */
117 write32(ch & 0xFF, base + UART_THR);
120 bool hi16xx_uart_have_rx_data(vaddr_t base)
122 return (read32(base + UART_USR) & UART_USR_RFNE_BIT);
125 int hi16xx_uart_getchar(vaddr_t base)
127 while (!hi16xx_uart_have_rx_data(base))
129 return read32(base + UART_RBR) & 0xFF;