2 * Copyright (c) 2016, Xilinx Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #include <drivers/cdns_uart.h>
32 #define CDNS_UART_CONTROL 0
33 #define CDNS_UART_MODE 4
34 #define CDNS_UART_IEN 8
35 #define CDNS_UART_IRQ_STATUS 0x14
36 #define CDNS_UART_CHANNEL_STATUS 0x2c
37 #define CDNS_UART_FIFO 0x30
39 #define CDNS_UART_CONTROL_RXRES BIT(0)
40 #define CDNS_UART_CONTROL_TXRES BIT(1)
41 #define CDNS_UART_CONTROL_RXEN BIT(2)
42 #define CDNS_UART_CONTROL_TXEN BIT(4)
44 #define CDNS_UART_MODE_8BIT (0 << 1)
45 #define CDNS_UART_MODE_PARITY_NONE (0x4 << 3)
46 #define CDNS_UART_MODE_1STP (0 << 6)
48 #define CDNS_UART_CHANNEL_STATUS_TFUL BIT(4)
49 #define CDNS_UART_CHANNEL_STATUS_TEMPTY BIT(3)
50 #define CDNS_UART_CHANNEL_STATUS_REMPTY BIT(1)
52 #define CDNS_UART_IRQ_RXTRIG BIT(0)
53 #define CDNS_UART_IRQ_RXTOUT BIT(8)
55 void cdns_uart_flush(vaddr_t base)
57 while (!(read32(base + CDNS_UART_CHANNEL_STATUS) &
58 CDNS_UART_CHANNEL_STATUS_TEMPTY))
63 * we rely on the bootloader having set up the HW correctly, we just enable
64 * transmitter/receiver here, just in case.
66 void cdns_uart_init(vaddr_t base, uint32_t uart_clk, uint32_t baud_rate)
68 if (!base || !uart_clk || !baud_rate)
71 /* Enable UART and RX/TX */
72 write32(CDNS_UART_CONTROL_RXEN | CDNS_UART_CONTROL_TXEN,
73 base + CDNS_UART_CONTROL);
75 cdns_uart_flush(base);
78 void cdns_uart_putc(int ch, vaddr_t base)
80 /* Wait until there is space in the FIFO */
81 while (read32(base + CDNS_UART_CHANNEL_STATUS) &
82 CDNS_UART_CHANNEL_STATUS_TFUL)
85 /* Send the character */
86 write32(ch, base + CDNS_UART_FIFO);
89 bool cdns_uart_have_rx_data(vaddr_t base)
91 return !(read32(base + CDNS_UART_CHANNEL_STATUS) &
92 CDNS_UART_CHANNEL_STATUS_REMPTY);
95 int cdns_uart_getchar(vaddr_t base)
97 while (!cdns_uart_have_rx_data(base))
99 return read32(base + CDNS_UART_FIFO) & 0xff;