2 * Copyright (c) 2014, STMicroelectronics International N.V.
3 * Copyright (c) 2015, Linaro Limited
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
9 * 1. Redistributions of source code must retain the above copyright notice,
10 * this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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28 #include <types_ext.h>
29 #include <utee_types.h>
30 #include <kernel/tee_ta_manager.h>
31 #include <mm/tee_mmu.h>
32 #include <mm/core_memprot.h>
34 #include "svc_cache.h"
37 * tee_uta_cache_operation - dynamic cache clean/inval request from a TA
38 * It follows ARM recommendation:
39 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246d/Beicdhde.html
40 * Note that this implementation assumes dsb operations are part of
41 * cache_maintenance_l1(), and L2 cache sync are part of
42 * cache_maintenance_l2()
44 static TEE_Result cache_operation(struct tee_ta_session *sess,
45 enum utee_cache_operation op, void *va, size_t len)
49 struct user_ta_ctx *utc = to_user_ta_ctx(sess->ctx);
51 if ((sess->ctx->flags & TA_FLAG_CACHE_MAINTENANCE) == 0)
52 return TEE_ERROR_NOT_SUPPORTED;
55 * TAs are allowed to operate cache maintenance on TA memref parameters
56 * only, not on the TA private memory.
58 if (tee_mmu_is_vbuf_intersect_ta_private(utc, va, len))
59 return TEE_ERROR_ACCESS_DENIED;
61 ret = tee_mmu_check_access_rights(utc, TEE_MEMORY_ACCESS_READ |
62 TEE_MEMORY_ACCESS_ANY_OWNER,
64 if (ret != TEE_SUCCESS)
65 return TEE_ERROR_ACCESS_DENIED;
67 pa = virt_to_phys(va);
69 return TEE_ERROR_ACCESS_DENIED;
73 /* Clean L1, Flush L2, Flush L1 */
74 ret = cache_maintenance_l1(DCACHE_AREA_CLEAN, va, len);
75 if (ret != TEE_SUCCESS)
77 ret = cache_maintenance_l2(L2CACHE_AREA_CLEAN_INV, pa, len);
78 if (ret != TEE_SUCCESS)
80 return cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, va, len);
83 /* Clean L1, Clean L2 */
84 ret = cache_maintenance_l1(DCACHE_AREA_CLEAN, va, len);
85 if (ret != TEE_SUCCESS)
87 return cache_maintenance_l2(L2CACHE_AREA_CLEAN, pa, len);
89 case TEE_CACHEINVALIDATE:
90 /* Inval L2, Inval L1 */
91 ret = cache_maintenance_l2(L2CACHE_AREA_INVALIDATE, pa, len);
92 if (ret != TEE_SUCCESS)
94 return cache_maintenance_l1(DCACHE_AREA_INVALIDATE, va, len);
97 return TEE_ERROR_NOT_SUPPORTED;
101 TEE_Result syscall_cache_operation(void *va, size_t len, unsigned long op)
104 struct tee_ta_session *s = NULL;
106 res = tee_ta_get_current_session(&s);
107 if (res != TEE_SUCCESS)
110 if ((s->ctx->flags & TA_FLAG_CACHE_MAINTENANCE) == 0)
111 return TEE_ERROR_NOT_SUPPORTED;
113 return cache_operation(s, op, va, len);