core/arch/arm/plat-zynq7k/main.c

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  * Copyright (c) 2016, Wind River Systems.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  18  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  21  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  27  * POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include <arm32.h>
  31 #include <console.h>
  32 #include <drivers/cdns_uart.h>
  33 #include <drivers/gic.h>
  34 #include <io.h>
  35 #include <kernel/generic_boot.h>
  36 #include <kernel/misc.h>
  37 #include <kernel/panic.h>
  38 #include <kernel/pm_stubs.h>
  39 #include <kernel/tz_ssvce_pl310.h>
  40 #include <mm/core_mmu.h>
  41 #include <mm/core_memprot.h>
  42 #include <platform_config.h>
  43 #include <platform_smc.h>
  44 #include <stdint.h>
  45 #include <tee/entry_fast.h>
  46 #include <tee/entry_std.h>
  47
  48 static void main_fiq(void);
  49 static void platform_tee_entry_fast(struct thread_smc_args *args);
  50
  51 static const struct thread_handlers handlers = {
  52         .std_smc = tee_entry_std,
  53         .fast_smc = platform_tee_entry_fast,
  54         .nintr = main_fiq,
  55         .cpu_on = pm_panic,
  56         .cpu_off = pm_panic,
  57         .cpu_suspend = pm_panic,
  58         .cpu_resume = pm_panic,
  59         .system_off = pm_panic,
  60         .system_reset = pm_panic,
  61 };
  62
  63 static struct gic_data gic_data;
  64 static struct cdns_uart_data console_data __early_bss;
  65
  66 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE);
  67 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE);
  68 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE);
  69 register_phys_mem(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_DEVICE_SIZE);
  70
  71 const struct thread_handlers *generic_boot_get_handlers(void)
  72 {
  73         return &handlers;
  74 }
  75
  76 static void main_fiq(void)
  77 {
  78         panic();
  79 }
  80
  81 void plat_cpu_reset_late(void)
  82 {
  83         if (!get_core_pos()) {
  84                 /* primary core */
  85 #if defined(CFG_BOOT_SECONDARY_REQUEST)
  86                 /* set secondary entry address and release core */
  87                 write32(CFG_TEE_LOAD_ADDR, SECONDARY_ENTRY_DROP);
  88                 dsb();
  89                 sev();
  90 #endif
  91
  92                 /* SCU config */
  93                 write32(SCU_INV_CTRL_INIT, SCU_BASE + SCU_INV_SEC);
  94                 write32(SCU_SAC_CTRL_INIT, SCU_BASE + SCU_SAC);
  95                 write32(SCU_NSAC_CTRL_INIT, SCU_BASE + SCU_NSAC);
  96
  97                 /* SCU enable */
  98                 write32(read32(SCU_BASE + SCU_CTRL) | 0x1,
  99                         SCU_BASE + SCU_CTRL);
 100
 101                 /* NS Access control */
 102                 write32(ACCESS_BITS_ALL, SECURITY2_SDIO0);
 103                 write32(ACCESS_BITS_ALL, SECURITY3_SDIO1);
 104                 write32(ACCESS_BITS_ALL, SECURITY4_QSPI);
 105                 write32(ACCESS_BITS_ALL, SECURITY6_APB_SLAVES);
 106
 107                 write32(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK);
 108
 109                 write32(ACCESS_BITS_ALL, SLCR_TZ_DDR_RAM);
 110                 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_NS);
 111                 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_IRQ_NS);
 112                 write32(ACCESS_BITS_ALL, SLCR_TZ_DMA_PERIPH_NS);
 113                 write32(ACCESS_BITS_ALL, SLCR_TZ_GEM);
 114                 write32(ACCESS_BITS_ALL, SLCR_TZ_SDIO);
 115                 write32(ACCESS_BITS_ALL, SLCR_TZ_USB);
 116
 117                 write32(SLCR_LOCK_MAGIC, SLCR_LOCK);
 118         }
 119 }
 120
 121 void console_init(void)
 122 {
 123         cdns_uart_init(&console_data, CONSOLE_UART_BASE, 0, 0);
 124         register_serial_console(&console_data.chip);
 125 }
 126
 127 vaddr_t pl310_base(void)
 128 {
 129         static void *va __early_bss;
 130
 131         if (cpu_mmu_enabled()) {
 132                 if (!va)
 133                         va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC);
 134                 return (vaddr_t)va;
 135         }
 136         return PL310_BASE;
 137 }
 138
 139 void arm_cl2_config(vaddr_t pl310_base)
 140 {
 141         /* Disable PL310 */
 142         write32(0, pl310_base + PL310_CTRL);
 143
 144         /*
 145          * Xilinx AR#54190 recommends setting L2C RAM in SLCR
 146          * to 0x00020202 for proper cache operations.
 147          */
 148         write32(SLCR_L2C_RAM_VALUE, SLCR_L2C_RAM);
 149
 150         write32(PL310_TAG_RAM_CTRL_INIT, pl310_base + PL310_TAG_RAM_CTRL);
 151         write32(PL310_DATA_RAM_CTRL_INIT, pl310_base + PL310_DATA_RAM_CTRL);
 152         write32(PL310_AUX_CTRL_INIT, pl310_base + PL310_AUX_CTRL);
 153         write32(PL310_PREFETCH_CTRL_INIT, pl310_base + PL310_PREFETCH_CTRL);
 154         write32(PL310_POWER_CTRL_INIT, pl310_base + PL310_POWER_CTRL);
 155
 156         /* invalidate all cache ways */
 157         arm_cl2_invbyway(pl310_base);
 158 }
 159
 160 void arm_cl2_enable(vaddr_t pl310_base)
 161 {
 162         uint32_t val;
 163
 164         /* Enable PL310 ctrl -> only set lsb bit */
 165         write32(1, pl310_base + PL310_CTRL);
 166
 167         /* if L2 FLZW enable, enable in L1 */
 168         val = read32(pl310_base + PL310_AUX_CTRL);
 169         if (val & 1)
 170                 write_actlr(read_actlr() | (1 << 3));
 171 }
 172
 173 void main_init_gic(void)
 174 {
 175         vaddr_t gicc_base;
 176         vaddr_t gicd_base;
 177
 178         gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET,
 179                                           MEM_AREA_IO_SEC);
 180         gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
 181                                           MEM_AREA_IO_SEC);
 182
 183         if (!gicc_base || !gicd_base)
 184                 panic();
 185
 186         /* Initialize GIC */
 187         gic_init(&gic_data, gicc_base, gicd_base);
 188         itr_init(&gic_data.chip);
 189 }
 190
 191 void main_secondary_init_gic(void)
 192 {
 193         gic_cpu_init(&gic_data);
 194 }
 195
 196 static vaddr_t slcr_access_range[] = {
 197         0x004, 0x008,   /* lock, unlock */
 198         0x100, 0x1FF,   /* PLL */
 199         0x200, 0x2FF,   /* Reset */
 200         0xA00, 0xAFF    /* L2C */
 201 };
 202
 203 static uint32_t write_slcr(uint32_t addr, uint32_t val)
 204 {
 205         uint32_t i;
 206
 207         for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) {
 208                 if (addr >= slcr_access_range[i] &&
 209                     addr <= slcr_access_range[i+1]) {
 210                         static vaddr_t va __early_bss;
 211
 212                         if (!va)
 213                                 va = (vaddr_t)phys_to_virt(SLCR_BASE,
 214                                                            MEM_AREA_IO_SEC);
 215                         write32(val, va + addr);
 216                         return OPTEE_SMC_RETURN_OK;
 217                 }
 218         }
 219         return OPTEE_SMC_RETURN_EBADADDR;
 220 }
 221
 222 static uint32_t read_slcr(uint32_t addr, uint32_t *val)
 223 {
 224         uint32_t i;
 225
 226         for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) {
 227                 if (addr >= slcr_access_range[i] &&
 228                     addr <= slcr_access_range[i+1]) {
 229                         static vaddr_t va __early_bss;
 230
 231                         if (!va)
 232                                 va = (vaddr_t)phys_to_virt(SLCR_BASE,
 233                                                            MEM_AREA_IO_SEC);
 234                         *val = read32(va + addr);
 235                         return OPTEE_SMC_RETURN_OK;
 236                 }
 237         }
 238         return OPTEE_SMC_RETURN_EBADADDR;
 239 }
 240
 241 static void platform_tee_entry_fast(struct thread_smc_args *args)
 242 {
 243         switch (args->a0) {
 244         case ZYNQ7K_SMC_SLCR_WRITE:
 245                 args->a0 = write_slcr(args->a1, args->a2);
 246                 break;
 247         case ZYNQ7K_SMC_SLCR_READ:
 248                 args->a0 = read_slcr(args->a1, &args->a2);
 249                 break;
 250         default:
 251                 tee_entry_fast(args);
 252                 break;
 253         }
 254 }