2 * Copyright (c) 2014, Linaro Limited
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #ifndef PLATFORM_CONFIG_H
29 #define PLATFORM_CONFIG_H
33 /* Make stacks aligned to data cache line length */
34 #define STACK_ALIGNMENT 64
38 #error "Pager not supported for ARM64"
42 #if defined(PLATFORM_FLAVOR_fvp)
44 #define GIC_BASE 0x2c000000
45 #define UART0_BASE 0x1c090000
46 #define UART1_BASE 0x1c0a0000
47 #define UART2_BASE 0x1c0b0000
48 #define UART3_BASE 0x1c0c0000
49 #define TZC400_BASE 0x2a4a0000
53 #define CONSOLE_UART_BASE UART1_BASE
54 #define IT_CONSOLE_UART IT_UART1
56 #elif defined(PLATFORM_FLAVOR_juno)
58 #define GIC_BASE 0x2c010000
61 #define UART0_BASE 0x1c090000
63 #define UART1_BASE 0x1c0a0000
65 #define UART2_BASE 0x7ff80000
67 #define UART3_BASE 0x7ff70000
70 #define UART0_CLK_IN_HZ 24000000
71 #define UART1_CLK_IN_HZ 24000000
72 #define UART2_CLK_IN_HZ 7273800
73 #define UART3_CLK_IN_HZ 7273800
78 #define CONSOLE_UART_BASE UART3_BASE
79 #define IT_CONSOLE_UART IT_UART3
80 #define CONSOLE_UART_CLK_IN_HZ UART3_CLK_IN_HZ
82 #elif defined(PLATFORM_FLAVOR_qemu_virt)
84 #define GIC_BASE 0x08000000
85 #define UART0_BASE 0x09000000
86 #define UART1_BASE 0x09040000
87 #define PCSC_BASE 0x09100000
92 #define CONSOLE_UART_BASE UART1_BASE
93 #define IT_CONSOLE_UART IT_UART1
95 #elif defined(PLATFORM_FLAVOR_qemu_armv8a)
97 #define UART0_BASE 0x09000000
98 #define UART1_BASE 0x09040000
100 #define CONSOLE_UART_BASE UART1_BASE
103 #error "Unknown platform flavor"
106 #if defined(PLATFORM_FLAVOR_fvp)
111 #define DRAM0_BASE 0x80000000
112 #define DRAM0_SIZE 0x80000000
114 #ifdef CFG_WITH_PAGER
117 #define TZSRAM_BASE (0x06000000)
118 #define TZSRAM_SIZE CFG_CORE_TZSRAM_EMUL_SIZE
120 #define TZDRAM_BASE (TZSRAM_BASE + CFG_TEE_RAM_VA_SIZE)
121 #define TZDRAM_SIZE (0x02000000 - CFG_TEE_RAM_VA_SIZE)
123 #else /*CFG_WITH_PAGER*/
125 /* Location of trusted dram on the base fvp */
126 #define TZDRAM_BASE 0x06000000
127 #define TZDRAM_SIZE 0x02000000
129 #endif /*CFG_WITH_PAGER*/
131 #define CFG_TEE_CORE_NB_CORE 8
133 #define CFG_SHMEM_START (DRAM0_BASE + 0x3000000)
134 #define CFG_SHMEM_SIZE 0x200000
136 #define GICC_OFFSET 0x0
137 #define GICD_OFFSET 0x3000000
139 #elif defined(PLATFORM_FLAVOR_juno)
144 #define DRAM0_BASE 0x80000000
145 #define DRAM0_SIZE 0x7F000000
147 #ifdef CFG_WITH_PAGER
150 #define TZSRAM_BASE 0xFF000000
151 #define TZSRAM_SIZE CFG_CORE_TZSRAM_EMUL_SIZE
153 #define TZDRAM_BASE (TZSRAM_BASE + CFG_TEE_RAM_VA_SIZE)
154 #define TZDRAM_SIZE (0x00E00000 - CFG_TEE_RAM_VA_SIZE)
156 #else /*CFG_WITH_PAGER*/
158 * Last part of DRAM is reserved as secure dram, note that the last 2MiB
159 * of DRAM0 is used by SCP dor DDR retraining.
161 #define TZDRAM_BASE 0xFF000000
164 * #define TZDRAM_SIZE 0x00FF8000
165 * but is smaller due to SECTION_SIZE alignment, can be fixed once
166 * OP-TEE OS is mapped using small pages instead.
168 #define TZDRAM_SIZE 0x00E00000
169 #endif /*CFG_WITH_PAGER*/
171 #define CFG_TEE_CORE_NB_CORE 6
173 #define CFG_SHMEM_START (DRAM0_BASE + DRAM0_SIZE - CFG_SHMEM_SIZE)
174 #define CFG_SHMEM_SIZE 0x200000
176 #define GICC_OFFSET 0x1f000
177 #define GICD_OFFSET 0
179 #elif defined(PLATFORM_FLAVOR_qemu_virt)
181 * QEMU virt specifics.
184 #define DRAM0_BASE UINTPTR_C(0x40000000)
185 #define DRAM0_SIZE (UINTPTR_C(0x42100000) - CFG_SHMEM_SIZE)
187 #define DRAM0_TEERES_BASE (DRAM0_BASE + DRAM0_SIZE)
188 #define DRAM0_TEERES_SIZE CFG_SHMEM_SIZE
190 #ifdef CFG_WITH_PAGER
193 #define TZSRAM_BASE 0x0e000000
194 #define TZSRAM_SIZE CFG_CORE_TZSRAM_EMUL_SIZE
196 #define TZDRAM_BASE (TZSRAM_BASE + TZSRAM_SIZE)
197 #define TZDRAM_SIZE (0x01000000 - TZSRAM_SIZE)
199 #else /* CFG_WITH_PAGER */
201 #define TZDRAM_BASE 0x0e000000
202 #define TZDRAM_SIZE 0x01000000
204 #endif /* CFG_WITH_PAGER */
207 #define CFG_TEE_CORE_NB_CORE 2
209 #define CFG_SHMEM_START (DRAM0_TEERES_BASE + \
210 (DRAM0_TEERES_SIZE - CFG_SHMEM_SIZE))
211 #define CFG_SHMEM_SIZE 0x200000
213 #define GICD_OFFSET 0
214 #define GICC_OFFSET 0x10000
217 #elif defined(PLATFORM_FLAVOR_qemu_armv8a)
219 #ifdef CFG_WITH_PAGER
220 #error "Pager not supported for platform vexpress-qemu_armv8a"
223 #define DRAM0_BASE UINTPTR_C(0x40000000)
224 #define DRAM0_SIZE (UINTPTR_C(0x40000000) - CFG_SHMEM_SIZE)
226 #define DRAM0_TEERES_BASE (DRAM0_BASE + DRAM0_SIZE)
227 #define DRAM0_TEERES_SIZE CFG_SHMEM_SIZE
229 #define TZDRAM_BASE 0x0e100000
230 #define TZDRAM_SIZE 0x00f00000
232 #define CFG_TEE_CORE_NB_CORE 2
234 #define CFG_SHMEM_START (DRAM0_TEERES_BASE + \
235 (DRAM0_TEERES_SIZE - CFG_SHMEM_SIZE))
236 #define CFG_SHMEM_SIZE 0x200000
239 #error "Unknown platform flavor"
242 #define CFG_TEE_RAM_VA_SIZE (1024 * 1024)
244 #ifndef CFG_TEE_LOAD_ADDR
245 #define CFG_TEE_LOAD_ADDR CFG_TEE_RAM_START
248 #ifdef CFG_WITH_PAGER
250 * Have TZSRAM either as real physical or emulated by reserving an area
253 * +------------------+
254 * | TZSRAM | TEE_RAM |
255 * +--------+---------+
256 * | TZDRAM | TA_RAM |
257 * +--------+---------+
259 #define CFG_TEE_RAM_PH_SIZE TZSRAM_SIZE
260 #define CFG_TEE_RAM_START TZSRAM_BASE
261 #define CFG_TA_RAM_START ROUNDUP(TZDRAM_BASE, CORE_MMU_DEVICE_SIZE)
262 #define CFG_TA_RAM_SIZE ROUNDDOWN(TZDRAM_SIZE, CORE_MMU_DEVICE_SIZE)
265 * Assumes that either TZSRAM isn't large enough or TZSRAM doesn't exist,
266 * everything is in TZDRAM.
267 * +------------------+
269 * + TZDRAM +---------+
271 * +--------+---------+
273 #define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE
274 #define CFG_TEE_RAM_START TZDRAM_BASE
275 #define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
276 CORE_MMU_DEVICE_SIZE)
277 #define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
278 CORE_MMU_DEVICE_SIZE)
282 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
283 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
286 #ifndef UART_BAUDRATE
287 #define UART_BAUDRATE 115200
289 #ifndef CONSOLE_BAUDRATE
290 #define CONSOLE_BAUDRATE UART_BAUDRATE
293 /* For virtual platforms where there isn't a clock */
294 #ifndef CONSOLE_UART_CLK_IN_HZ
295 #define CONSOLE_UART_CLK_IN_HZ 1
298 #endif /*PLATFORM_CONFIG_H*/