2 * Copyright (c) 2016, Linaro Limited
3 * Copyright (c) 2014, STMicroelectronics International N.V.
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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29 #include <platform_config.h>
34 #include <drivers/gic.h>
35 #include <drivers/pl011.h>
36 #include <drivers/tzc400.h>
39 #include <kernel/generic_boot.h>
40 #include <kernel/pm_stubs.h>
42 #include <kernel/misc.h>
43 #include <kernel/panic.h>
44 #include <kernel/tee_time.h>
45 #include <tee/entry_fast.h>
46 #include <tee/entry_std.h>
47 #include <mm/core_memprot.h>
48 #include <mm/core_mmu.h>
53 static void main_fiq(void);
55 static const struct thread_handlers handlers = {
56 .std_smc = tee_entry_std,
57 .fast_smc = tee_entry_fast,
59 #if defined(CFG_WITH_ARM_TRUSTED_FW)
60 .cpu_on = cpu_on_handler,
61 .cpu_off = pm_do_nothing,
62 .cpu_suspend = pm_do_nothing,
63 .cpu_resume = pm_do_nothing,
64 .system_off = pm_do_nothing,
65 .system_reset = pm_do_nothing,
69 .cpu_suspend = pm_panic,
70 .cpu_resume = pm_panic,
71 .system_off = pm_panic,
72 .system_reset = pm_panic,
76 static struct gic_data gic_data;
77 static struct pl011_data console_data __early_bss;
79 register_phys_mem(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
81 const struct thread_handlers *generic_boot_get_handlers(void)
88 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
89 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
91 void main_init_gic(void)
96 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET,
98 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
100 if (!gicc_base || !gicd_base)
103 #if defined(PLATFORM_FLAVOR_fvp) || defined(PLATFORM_FLAVOR_juno) || \
104 defined(PLATFORM_FLAVOR_qemu_armv8a)
105 /* On ARMv8, GIC configuration is initialized in ARM-TF */
106 gic_init_base_addr(&gic_data, gicc_base, gicd_base);
109 gic_init(&gic_data, gicc_base, gicd_base);
111 itr_init(&gic_data.chip);
115 static void main_fiq(void)
117 gic_it_handle(&gic_data);
120 void console_init(void)
122 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
124 register_serial_console(&console_data.chip);
127 #ifdef IT_CONSOLE_UART
128 static enum itr_return console_itr_cb(struct itr_handler *h __unused)
130 struct serial_chip *cons = &console_data.chip;
132 while (cons->ops->have_rx_data(cons)) {
133 int ch __maybe_unused = cons->ops->getchar(cons);
135 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch);
140 static struct itr_handler console_itr = {
141 .it = IT_CONSOLE_UART,
142 .flags = ITRF_TRIGGER_LEVEL,
143 .handler = console_itr_cb,
145 KEEP_PAGER(console_itr);
147 static TEE_Result init_console_itr(void)
149 itr_add(&console_itr);
150 itr_enable(IT_CONSOLE_UART);
153 driver_init(init_console_itr);
157 register_phys_mem(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE);
159 static TEE_Result init_tzc400(void)
163 DMSG("Initializing TZC400");
165 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC);
167 EMSG("TZC400 not mapped");
171 tzc_init((vaddr_t)va);
177 service_init(init_tzc400);
178 #endif /*CFG_TZC400*/