2 * Copyright (c) 2015, Linaro Limited
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
28 #ifndef PLATFORM_CONFIG_H
29 #define PLATFORM_CONFIG_H
31 #if defined(PLATFORM_FLAVOR_dra7xx) || defined(PLATFORM_FLAVOR_am57xx)
33 #define DRAM0_BASE 0xbe000000
34 #define DRAM0_SIZE 0x02000000
37 #error Pager not supported on this platform
38 #endif /*CFG_WITH_PAGER*/
40 /* Location of protected DDR on the DRA7xx platform */
41 #define TZDRAM_BASE 0xbe000000
42 #define TZDRAM_SIZE 0x01c00000
44 #define CFG_TEE_CORE_NB_CORE 2
46 #define UART1_BASE 0x4806A000
47 #define UART2_BASE 0x4806C000
48 #define UART3_BASE 0x48020000
51 #define CONSOLE_UART_BASE UART1_BASE
52 #define CONSOLE_BAUDRATE 115200
53 #define CONSOLE_UART_CLK_IN_HZ 48000000
55 #define GIC_BASE 0x48210000
56 #define GICC_OFFSET 0x2000
57 #define GICC_SIZE 0x1000
58 #define GICD_OFFSET 0x1000
59 #define GICD_SIZE 0x1000
60 #define GICC_BASE (GIC_BASE + GICC_OFFSET)
61 #define GICD_BASE (GIC_BASE + GICD_OFFSET)
63 #define SECRAM_BASE 0x40200000
66 #define RNG_BASE 0x48090000
69 #error "Unknown platform flavor"
72 #if defined(PLATFORM_FLAVOR_am57xx)
75 #undef CONSOLE_UART_BASE
76 #define CONSOLE_UART_BASE UART3_BASE
80 /* Make stacks aligned to data cache line length */
81 #define STACK_ALIGNMENT 64
83 /* Full GlobalPlatform test suite requires CFG_SHMEM_SIZE to be at least 2MB */
84 #define CFG_SHMEM_START (DRAM0_BASE + TZDRAM_SIZE)
85 #define CFG_SHMEM_SIZE 0x400000
87 #define CFG_TEE_RAM_VA_SIZE (1024 * 1024)
89 #ifndef CFG_TEE_LOAD_ADDR
90 #define CFG_TEE_LOAD_ADDR (CFG_TEE_RAM_START + 0x100)
94 * Assumes that either TZSRAM isn't large enough or TZSRAM doesn't exist,
95 * everything is in TZDRAM.
96 * +------------------+
98 * + TZDRAM +---------+
100 * +--------+---------+
102 #define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE
103 #define CFG_TEE_RAM_START TZDRAM_BASE
104 #define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
105 CORE_MMU_DEVICE_SIZE)
106 #define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
107 CORE_MMU_DEVICE_SIZE)
109 #define DEVICE2_PA_BASE ROUNDDOWN(SECRAM_BASE, CORE_MMU_DEVICE_SIZE)
110 #define DEVICE2_VA_BASE DEVICE2_PA_BASE
111 #define DEVICE2_SIZE CORE_MMU_DEVICE_SIZE
112 #define DEVICE2_TYPE MEM_AREA_IO_SEC
114 #endif /*PLATFORM_CONFIG_H*/