2 * Copyright (c) 2015, Linaro Limited
5 * Redistribution and use in source and binary forms, with or without
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9 * this list of conditions and the following disclaimer.
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12 * this list of conditions and the following disclaimer in the documentation
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15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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28 #include <platform_config.h>
33 #include <drivers/gic.h>
35 #include <kernel/generic_boot.h>
36 #include <kernel/panic.h>
37 #include <kernel/pm_stubs.h>
39 #include <kernel/misc.h>
40 #include <kernel/mutex.h>
41 #include <kernel/tee_time.h>
42 #include <mm/core_mmu.h>
43 #include <mm/core_memprot.h>
44 #include <tee/entry_std.h>
45 #include <tee/entry_fast.h>
49 static struct gic_data gic_data;
51 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE);
52 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);
54 void main_init_gic(void)
59 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC);
60 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC);
62 if (!gicc_base || !gicd_base)
65 gic_init(&gic_data, gicc_base, gicd_base);
66 itr_init(&gic_data.chip);
69 void main_secondary_init_gic(void)
71 gic_cpu_init(&gic_data);
74 static void main_fiq(void)
76 gic_it_handle(&gic_data);
79 static const struct thread_handlers handlers = {
80 .std_smc = tee_entry_std,
81 .fast_smc = tee_entry_fast,
85 .cpu_suspend = pm_panic,
86 .cpu_resume = pm_panic,
87 .system_off = pm_panic,
88 .system_reset = pm_panic,
91 const struct thread_handlers *generic_boot_get_handlers(void)
96 struct plat_nsec_ctx {
119 void init_sec_mon(unsigned long nsec_entry)
121 struct plat_nsec_ctx *plat_ctx;
122 struct sm_nsec_ctx *nsec_ctx;
124 plat_ctx = phys_to_virt(nsec_entry, MEM_AREA_IO_SEC);
128 /* Invalidate cache to fetch data from external memory */
129 cache_maintenance_l1(DCACHE_AREA_INVALIDATE,
130 plat_ctx, sizeof(*plat_ctx));
132 /* Initialize secure monitor */
133 nsec_ctx = sm_get_nsec_ctx();
135 nsec_ctx->mode_regs.usr_sp = plat_ctx->usr_sp;
136 nsec_ctx->mode_regs.usr_lr = plat_ctx->usr_lr;
137 nsec_ctx->mode_regs.irq_spsr = plat_ctx->irq_spsr;
138 nsec_ctx->mode_regs.irq_sp = plat_ctx->irq_sp;
139 nsec_ctx->mode_regs.irq_lr = plat_ctx->irq_lr;
140 nsec_ctx->mode_regs.svc_spsr = plat_ctx->svc_spsr;
141 nsec_ctx->mode_regs.svc_sp = plat_ctx->svc_sp;
142 nsec_ctx->mode_regs.svc_lr = plat_ctx->svc_lr;
143 nsec_ctx->mode_regs.abt_spsr = plat_ctx->abt_spsr;
144 nsec_ctx->mode_regs.abt_sp = plat_ctx->abt_sp;
145 nsec_ctx->mode_regs.abt_lr = plat_ctx->abt_lr;
146 nsec_ctx->mode_regs.und_spsr = plat_ctx->und_spsr;
147 nsec_ctx->mode_regs.und_sp = plat_ctx->und_sp;
148 nsec_ctx->mode_regs.und_lr = plat_ctx->und_lr;
149 nsec_ctx->mon_lr = plat_ctx->mon_lr;
150 nsec_ctx->mon_spsr = plat_ctx->mon_spsr;