2 * Copyright (c) 2015, Linaro Limited
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 #include <platform_config.h>
33 #include <drivers/gic.h>
34 #include <drivers/serial8250_uart.h>
36 #include <kernel/generic_boot.h>
37 #include <kernel/panic.h>
38 #include <kernel/pm_stubs.h>
40 #include <kernel/misc.h>
41 #include <kernel/mutex.h>
42 #include <kernel/tee_time.h>
43 #include <mm/core_mmu.h>
44 #include <mm/core_memprot.h>
45 #include <tee/entry_std.h>
46 #include <tee/entry_fast.h>
50 static struct gic_data gic_data;
51 static struct serial8250_uart_data console_data __early_bss;
53 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE);
54 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);
55 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
56 SERIAL8250_UART_REG_SIZE);
58 void main_init_gic(void)
63 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC);
64 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC);
66 if (!gicc_base || !gicd_base)
69 gic_init(&gic_data, gicc_base, gicd_base);
70 itr_init(&gic_data.chip);
73 void main_secondary_init_gic(void)
75 gic_cpu_init(&gic_data);
78 static void main_fiq(void)
80 gic_it_handle(&gic_data);
83 static const struct thread_handlers handlers = {
84 .std_smc = tee_entry_std,
85 .fast_smc = tee_entry_fast,
89 .cpu_suspend = pm_panic,
90 .cpu_resume = pm_panic,
91 .system_off = pm_panic,
92 .system_reset = pm_panic,
95 const struct thread_handlers *generic_boot_get_handlers(void)
100 struct plat_nsec_ctx {
123 void init_sec_mon(unsigned long nsec_entry)
125 struct plat_nsec_ctx *plat_ctx;
126 struct sm_nsec_ctx *nsec_ctx;
128 plat_ctx = phys_to_virt(nsec_entry, MEM_AREA_IO_SEC);
132 /* Invalidate cache to fetch data from external memory */
133 cache_op_inner(DCACHE_AREA_INVALIDATE,
134 plat_ctx, sizeof(*plat_ctx));
136 /* Initialize secure monitor */
137 nsec_ctx = sm_get_nsec_ctx();
139 nsec_ctx->mode_regs.usr_sp = plat_ctx->usr_sp;
140 nsec_ctx->mode_regs.usr_lr = plat_ctx->usr_lr;
141 nsec_ctx->mode_regs.irq_spsr = plat_ctx->irq_spsr;
142 nsec_ctx->mode_regs.irq_sp = plat_ctx->irq_sp;
143 nsec_ctx->mode_regs.irq_lr = plat_ctx->irq_lr;
144 nsec_ctx->mode_regs.svc_spsr = plat_ctx->svc_spsr;
145 nsec_ctx->mode_regs.svc_sp = plat_ctx->svc_sp;
146 nsec_ctx->mode_regs.svc_lr = plat_ctx->svc_lr;
147 nsec_ctx->mode_regs.abt_spsr = plat_ctx->abt_spsr;
148 nsec_ctx->mode_regs.abt_sp = plat_ctx->abt_sp;
149 nsec_ctx->mode_regs.abt_lr = plat_ctx->abt_lr;
150 nsec_ctx->mode_regs.und_spsr = plat_ctx->und_spsr;
151 nsec_ctx->mode_regs.und_sp = plat_ctx->und_sp;
152 nsec_ctx->mode_regs.und_lr = plat_ctx->und_lr;
153 nsec_ctx->mon_lr = plat_ctx->mon_lr;
154 nsec_ctx->mon_spsr = plat_ctx->mon_spsr;
157 void console_init(void)
159 serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
160 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
161 register_serial_console(&console_data.chip);