2 * Copyright (c) 2014, Allwinner Technology Co., Ltd.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
27 #include <platform_config.h>
30 #include <sm/tee_mon.h>
31 #include <sm/optee_smc.h>
32 #include <optee_msg.h>
35 #include <kernel/thread.h>
36 #include <kernel/time_source.h>
37 #include <kernel/panic.h>
38 #include <kernel/misc.h>
39 #include <mm/tee_pager.h>
40 #include <mm/core_mmu.h>
41 #include <mm/core_memprot.h>
43 #include <drivers/gic.h>
44 #include <drivers/sunxi_uart.h>
53 void sunxi_secondary_entry(void);
55 uint32_t sunxi_secondary_ns_entry;
57 struct gic_data gic_data;
59 static int platform_smp_init(void)
61 vaddr_t base = (vaddr_t)phys_to_virt(PRCM_BASE, MEM_AREA_IO_SEC);
64 write32((uint32_t)sunxi_secondary_entry,
65 base + PRCM_CPU_SOFT_ENTRY_REG);
70 void platform_init(void)
76 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET,
78 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
80 cci400_base = (vaddr_t)phys_to_virt(CCI400_BASE, MEM_AREA_IO_SEC);
81 if (!gicc_base || !gicd_base || !cci400_base)
85 * GIC configuration is initialized in Secure bootloader,
86 * Initialize GIC base address here for debugging.
88 gic_init_base_addr(&gic_data, gicc_base, gicd_base);
89 itr_init(&gic_data.chip);
91 /* platform smp initialize */
94 /* enable non-secure access cci-400 registers */
95 write32(0x1, cci400_base + CCI400_SECURE_ACCESS_REG);
104 * handle platform special smc commands.
106 uint32_t platform_smc_handle(struct thread_smc_args *smc_args)
108 uint32_t ret = TEE_SUCCESS;
109 switch (smc_args->a1) {
110 case OPTEE_SMC_SIP_SUNXI_SET_SMP_BOOTENTRY:
111 sunxi_secondary_ns_entry = smc_args->a2;
113 /* in order to sync with secondary up cpu */
114 cache_maintenance_l1(DCACHE_AREA_CLEAN,
115 (void *)(&sunxi_secondary_ns_entry),
119 ret = OPTEE_SMC_RETURN_EBADCMD;