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29 #include <arm32_macros.S>
30 #include <arm32_macros_cortex_a9.S>
32 #include <kernel/tz_ssvce_def.h>
33 #include <kernel/unwind.h>
34 #include <platform_config.h>
41 * void arm_cl2_enable(vaddr_t pl310_base) - Memory Cache Level2 Enable Function
43 * If PL310 supports FZLW, enable also FZL in A9 core
45 * Use scratables registers R0-R3.
47 * LR store return address.
48 * Trap CPU in case of error.
49 * TODO: to be moved to PL310 code (tz_svce_pl310.S ?)
51 FUNC arm_cl2_enable , :
54 /* Enable PL310 ctrl -> only set lsb bit */
56 str r1, [r0, #PL310_CTRL]
58 /* if L2 FLZW enable, enable in L1 */
59 ldr r1, [r0, #PL310_AUX_CTRL]
60 tst r1, #(1 << 0) /* test AUX_CTRL[FLZ] */
62 orrne r0, r0, #(1 << 3) /* enable ACTLR[FLZW] */
68 END_FUNC arm_cl2_enable
71 * Cortex A9 configuration early configuration
73 * Use scratables registers R0-R3.
75 * LR store return address.
76 * Trap CPU in case of error.
78 FUNC plat_cpu_reset_early , :
81 mov_imm r0, CPU_SCTLR_INIT
84 mov_imm r0, CPU_ACTLR_INIT
87 mov_imm r0, CPU_NSACR_INIT
90 mov_imm r0, CPU_PCR_INIT
96 END_FUNC plat_cpu_reset_early