2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
5 * Peng Fan <peng.fan@nxp.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
30 #include <drivers/imx_uart.h>
32 #include <kernel/generic_boot.h>
33 #include <kernel/panic.h>
34 #include <kernel/pm_stubs.h>
35 #include <mm/core_mmu.h>
36 #include <mm/core_memprot.h>
37 #include <platform_config.h>
39 #include <sm/optee_smc.h>
41 #include <tee/entry_std.h>
42 #include <tee/entry_fast.h>
44 static vaddr_t src_base(void)
46 /* in case it's used before .bss is cleared */
47 static void *va __early_bss;
49 if (cpu_mmu_enabled()) {
51 va = phys_to_virt(SRC_BASE, MEM_AREA_IO_SEC);
57 int psci_cpu_on(uint32_t core_idx, uint32_t entry,
58 uint32_t context_id __attribute__((unused)))
61 vaddr_t va = src_base();
63 if ((core_idx == 0) || (core_idx >= CFG_TEE_CORE_NB_CORE))
64 return PSCI_RET_INVALID_PARAMETERS;
66 /* set secondary cores' NS entry addresses */
67 ns_entry_addrs[core_idx] = entry;
69 /* boot secondary cores from OP-TEE load address */
70 write32((uint32_t)CFG_TEE_LOAD_ADDR, va + SRC_GPR1 + core_idx * 8);
72 /* release secondary core */
73 val = read32(va + SRC_SCR);
74 val |= BIT32(SRC_SCR_CORE1_ENABLE_OFFSET + (core_idx - 1));
75 val |= BIT32(SRC_SCR_CORE1_RST_OFFSET + (core_idx - 1));
76 write32(val, va + SRC_SCR);
78 return PSCI_RET_SUCCESS;