core/arch/arm/plat-imx/main.c

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  * Copyright (c) 2016, Wind River Systems.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright notice,
  14  * this list of conditions and the following disclaimer in the documentation
  15  * and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  18  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  21  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  27  * POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include <arm32.h>
  31 #include <console.h>
  32 #include <drivers/gic.h>
  33 #include <drivers/imx_uart.h>
  34 #include <io.h>
  35 #include <kernel/generic_boot.h>
  36 #include <kernel/misc.h>
  37 #include <kernel/panic.h>
  38 #include <kernel/pm_stubs.h>
  39 #include <mm/core_mmu.h>
  40 #include <mm/core_memprot.h>
  41 #include <platform_config.h>
  42 #include <stdint.h>
  43 #include <sm/optee_smc.h>
  44 #include <tee/entry_fast.h>
  45 #include <tee/entry_std.h>
  46
  47 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \
  48         defined(PLATFORM_FLAVOR_mx6qsabresd) || \
  49         defined(PLATFORM_FLAVOR_mx6dlsabresd)
  50 #include <kernel/tz_ssvce_pl310.h>
  51 #endif
  52
  53 static void main_fiq(void);
  54 static struct gic_data gic_data;
  55
  56 static const struct thread_handlers handlers = {
  57         .std_smc = tee_entry_std,
  58         .fast_smc = tee_entry_fast,
  59         .nintr = main_fiq,
  60         .cpu_on = pm_panic,
  61         .cpu_off = pm_panic,
  62         .cpu_suspend = pm_panic,
  63         .cpu_resume = pm_panic,
  64         .system_off = pm_panic,
  65         .system_reset = pm_panic,
  66 };
  67
  68 static struct imx_uart_data console_data __early_bss;
  69
  70 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE);
  71 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE);
  72
  73 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \
  74         defined(PLATFORM_FLAVOR_mx6qsabresd) || \
  75         defined(PLATFORM_FLAVOR_mx6dlsabresd)
  76 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE);
  77 register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, CORE_MMU_DEVICE_SIZE);
  78 #endif
  79
  80 const struct thread_handlers *generic_boot_get_handlers(void)
  81 {
  82         return &handlers;
  83 }
  84
  85 static void main_fiq(void)
  86 {
  87         panic();
  88 }
  89
  90 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \
  91         defined(PLATFORM_FLAVOR_mx6qsabresd) || \
  92         defined(PLATFORM_FLAVOR_mx6dlsabresd)
  93 void plat_cpu_reset_late(void)
  94 {
  95         uintptr_t addr;
  96
  97         if (!get_core_pos()) {
  98                 /* primary core */
  99 #if defined(CFG_BOOT_SYNC_CPU)
 100                 /* set secondary entry address and release core */
 101                 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 8);
 102                 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 16);
 103                 write32(CFG_TEE_LOAD_ADDR, SRC_BASE + SRC_GPR1 + 24);
 104
 105                 write32(SRC_SCR_CPU_ENABLE_ALL, SRC_BASE + SRC_SCR);
 106 #endif
 107
 108                 /* SCU config */
 109                 write32(SCU_INV_CTRL_INIT, SCU_BASE + SCU_INV_SEC);
 110                 write32(SCU_SAC_CTRL_INIT, SCU_BASE + SCU_SAC);
 111                 write32(SCU_NSAC_CTRL_INIT, SCU_BASE + SCU_NSAC);
 112
 113                 /* SCU enable */
 114                 write32(read32(SCU_BASE + SCU_CTRL) | 0x1,
 115                         SCU_BASE + SCU_CTRL);
 116
 117                 /* configure imx6 CSU */
 118
 119                 /* first grant all peripherals */
 120                 for (addr = CSU_BASE + CSU_CSL_START;
 121                          addr != CSU_BASE + CSU_CSL_END;
 122                          addr += 4)
 123                         write32(CSU_ACCESS_ALL, addr);
 124
 125                 /* lock the settings */
 126                 for (addr = CSU_BASE + CSU_CSL_START;
 127                          addr != CSU_BASE + CSU_CSL_END;
 128                          addr += 4)
 129                         write32(read32(addr) | CSU_SETTING_LOCK, addr);
 130         }
 131 }
 132 #endif
 133
 134 void console_init(void)
 135 {
 136         imx_uart_init(&console_data, CONSOLE_UART_BASE);
 137         register_serial_console(&console_data.chip);
 138 }
 139
 140 void main_init_gic(void)
 141 {
 142         vaddr_t gicc_base;
 143         vaddr_t gicd_base;
 144
 145         gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET,
 146                                           MEM_AREA_IO_SEC);
 147         gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
 148                                           MEM_AREA_IO_SEC);
 149
 150         if (!gicc_base || !gicd_base)
 151                 panic();
 152
 153         /* Initialize GIC */
 154         gic_init(&gic_data, gicc_base, gicd_base);
 155         itr_init(&gic_data.chip);
 156 }
 157
 158 #if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \
 159         defined(PLATFORM_FLAVOR_mx6qsabresd) || \
 160         defined(PLATFORM_FLAVOR_mx6dlsabresd)
 161 vaddr_t pl310_base(void)
 162 {
 163         static void *va __early_bss;
 164
 165         if (cpu_mmu_enabled()) {
 166                 if (!va)
 167                         va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC);
 168                 return (vaddr_t)va;
 169         }
 170         return PL310_BASE;
 171 }
 172
 173 void main_secondary_init_gic(void)
 174 {
 175         gic_cpu_init(&gic_data);
 176 }
 177 #endif