2 * Copyright (c) 2016, Linaro Limited
3 * Copyright (c) 2014, STMicroelectronics International N.V.
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32 #include <kernel/user_ta.h>
33 #include <mm/tee_mmu_types.h>
34 #include <types_ext.h>
36 /* A small page is the smallest unit of memory that can be mapped */
37 #define SMALL_PAGE_SHIFT 12
38 #define SMALL_PAGE_MASK 0x00000fff
39 #define SMALL_PAGE_SIZE 0x00001000
42 * PGDIR is the translation table above the translation table that holds
46 #define CORE_MMU_PGDIR_SHIFT 21
48 #define CORE_MMU_PGDIR_SHIFT 20
50 #define CORE_MMU_PGDIR_SIZE (1 << CORE_MMU_PGDIR_SHIFT)
51 #define CORE_MMU_PGDIR_MASK (CORE_MMU_PGDIR_SIZE - 1)
53 /* Devices are mapped using this granularity */
54 #define CORE_MMU_DEVICE_SHIFT CORE_MMU_PGDIR_SHIFT
55 #define CORE_MMU_DEVICE_SIZE (1 << CORE_MMU_DEVICE_SHIFT)
56 #define CORE_MMU_DEVICE_MASK (CORE_MMU_DEVICE_SIZE - 1)
58 /* TA user space code, data, stack and heap are mapped using this granularity */
59 #ifdef CFG_SMALL_PAGE_USER_TA
60 #define CORE_MMU_USER_CODE_SHIFT SMALL_PAGE_SHIFT
62 #define CORE_MMU_USER_CODE_SHIFT CORE_MMU_PGDIR_SHIFT
64 #define CORE_MMU_USER_CODE_SIZE (1 << CORE_MMU_USER_CODE_SHIFT)
65 #define CORE_MMU_USER_CODE_MASK (CORE_MMU_USER_CODE_SIZE - 1)
67 /* TA user space parameters are mapped using this granularity */
68 #ifdef CFG_SMALL_PAGE_USER_TA
69 #define CORE_MMU_USER_PARAM_SHIFT SMALL_PAGE_SHIFT
71 #define CORE_MMU_USER_PARAM_SHIFT CORE_MMU_PGDIR_SHIFT
73 #define CORE_MMU_USER_PARAM_SIZE (1 << CORE_MMU_USER_PARAM_SHIFT)
74 #define CORE_MMU_USER_PARAM_MASK (CORE_MMU_USER_PARAM_SIZE - 1)
78 * MEM_AREA_NOTYPE: Undefined type. Used as end of table.
79 * MEM_AREA_TEE_RAM: teecore execution RAM (secure, reserved to TEE, unused)
80 * MEM_AREA_TEE_COHERENT: teecore coherent RAM (secure, reserved to TEE)
81 * MEM_AREA_TA_RAM: Secure RAM where teecore loads/exec TA instances.
82 * MEM_AREA_NSEC_SHM: NonSecure shared RAM between NSec and TEE.
83 * MEM_AREA_RAM_NSEC: NonSecure RAM storing data
84 * MEM_AREA_RAM_SEC: Secure RAM storing some secrets
85 * MEM_AREA_IO_NSEC: NonSecure HW mapped registers
86 * MEM_AREA_IO_SEC: Secure HW mapped registers
87 * MEM_AREA_RES_VASPACE: Reserved virtual memory space
88 * MEM_AREA_TA_VASPACE: TA va space, only used with phys_to_virt()
89 * MEM_AREA_MAXTYPE: lower invalid 'type' value
91 enum teecore_memtypes {
94 MEM_AREA_TEE_COHERENT,
101 MEM_AREA_RES_VASPACE,
106 struct core_mmu_phys_mem {
108 enum teecore_memtypes type;
113 #define register_phys_mem(type, addr, size) \
114 static const struct core_mmu_phys_mem __phys_mem_ ## addr \
115 __used __section("phys_mem_map_section") = \
116 { #addr, (type), (addr), (size) }
119 /* Default NSec shared memory allocated from NSec world */
120 extern unsigned long default_nsec_shm_paddr;
121 extern unsigned long default_nsec_shm_size;
123 void core_init_mmu_map(void);
124 void core_init_mmu_regs(void);
126 bool core_mmu_place_tee_ram_at_top(paddr_t paddr);
130 * struct core_mmu_user_map - current user mapping register state
131 * @user_map: physical address of user map translation table
132 * @asid: ASID for the user map
134 * Note that this struct should be treated as an opaque struct since
135 * the content depends on descriptor table format.
137 struct core_mmu_user_map {
143 * struct core_mmu_user_map - current user mapping register state
144 * @ttbr0: content of ttbr0
145 * @ctxid: content of contextidr
147 * Note that this struct should be treated as an opaque struct since
148 * the content depends on descriptor table format.
150 struct core_mmu_user_map {
157 bool core_mmu_user_va_range_is_defined(void);
159 static inline bool core_mmu_user_va_range_is_defined(void)
166 * core_mmu_get_user_va_range() - Return range of user va space
167 * @base: Lowest user virtual address
168 * @size: Size in bytes of user address space
170 void core_mmu_get_user_va_range(vaddr_t *base, size_t *size);
173 * enum core_mmu_fault - different kinds of faults
174 * @CORE_MMU_FAULT_ALIGNMENT: alignment fault
175 * @CORE_MMU_FAULT_DEBUG_EVENT: debug event
176 * @CORE_MMU_FAULT_TRANSLATION: translation fault
177 * @CORE_MMU_FAULT_WRITE_PERMISSION: Permission fault during write
178 * @CORE_MMU_FAULT_READ_PERMISSION: Permission fault during read
179 * @CORE_MMU_FAULT_ASYNC_EXTERNAL: asynchronous external abort
180 * @CORE_MMU_FAULT_ACCESS_BIT: access bit fault
181 * @CORE_MMU_FAULT_OTHER: Other/unknown fault
183 enum core_mmu_fault {
184 CORE_MMU_FAULT_ALIGNMENT,
185 CORE_MMU_FAULT_DEBUG_EVENT,
186 CORE_MMU_FAULT_TRANSLATION,
187 CORE_MMU_FAULT_WRITE_PERMISSION,
188 CORE_MMU_FAULT_READ_PERMISSION,
189 CORE_MMU_FAULT_ASYNC_EXTERNAL,
190 CORE_MMU_FAULT_ACCESS_BIT,
191 CORE_MMU_FAULT_OTHER,
195 * core_mmu_get_fault_type() - get fault type
196 * @fault_descr: Content of fault status or exception syndrome register
197 * @returns an enum describing the content of fault status register.
199 enum core_mmu_fault core_mmu_get_fault_type(uint32_t fault_descr);
202 * core_mm_type_to_attr() - convert memory type to attribute
204 * @returns an attribute that can be passed to core_mm_set_entry() and friends
206 uint32_t core_mmu_type_to_attr(enum teecore_memtypes t);
209 * core_mmu_create_user_map() - Create user space mapping
210 * @utc: Pointer to user TA context
211 * @map: MMU configuration to use when activating this VA space
213 void core_mmu_create_user_map(struct user_ta_ctx *utc,
214 struct core_mmu_user_map *map);
216 * core_mmu_get_user_map() - Reads current MMU configuration for user VA space
217 * @map: MMU configuration for current user VA space.
219 void core_mmu_get_user_map(struct core_mmu_user_map *map);
222 * core_mmu_set_user_map() - Set new MMU configuration for user VA space
223 * @map: If NULL will disable user VA space, if not NULL the user
224 * VA space to activate.
226 void core_mmu_set_user_map(struct core_mmu_user_map *map);
229 * struct core_mmu_table_info - Properties for a translation table
230 * @table: Pointer to translation table
231 * @va_base: VA base address of the transaltion table
232 * @level: Translation table level
233 * @shift: The shift of each entry in the table
234 * @num_entries: Number of entries in this table.
236 struct core_mmu_table_info {
241 unsigned num_entries;
245 * core_mmu_find_table() - Locates a translation table
246 * @va: Virtual address for the table to cover
247 * @max_level: Don't traverse beyond this level
248 * @tbl_info: Pointer to where to store properties.
249 * @return true if a translation table was found, false on error
251 bool core_mmu_find_table(vaddr_t va, unsigned max_level,
252 struct core_mmu_table_info *tbl_info);
255 * core_mmu_divide_block() - divide larger block/section into smaller ones
256 * @tbl_info: table where target record located
257 * @idx: index of record
258 * @return true if function was able to divide block, false on error
260 bool core_mmu_divide_block(struct core_mmu_table_info *tbl_info,
263 void core_mmu_set_entry_primitive(void *table, size_t level, size_t idx,
264 paddr_t pa, uint32_t attr);
266 void core_mmu_get_user_pgdir(struct core_mmu_table_info *pgd_info);
269 * core_mmu_set_entry() - Set entry in translation table
270 * @tbl_info: Translation table properties
271 * @idx: Index of entry to update
272 * @pa: Physical address to assign entry
273 * @attr: Attributes to assign entry
275 void core_mmu_set_entry(struct core_mmu_table_info *tbl_info, unsigned idx,
276 paddr_t pa, uint32_t attr);
278 void core_mmu_get_entry_primitive(const void *table, size_t level, size_t idx,
279 paddr_t *pa, uint32_t *attr);
282 * core_mmu_get_entry() - Get entry from translation table
283 * @tbl_info: Translation table properties
284 * @idx: Index of entry to read
285 * @pa: Physical address is returned here if pa is not NULL
286 * @attr: Attributues are returned here if attr is not NULL
288 void core_mmu_get_entry(struct core_mmu_table_info *tbl_info, unsigned idx,
289 paddr_t *pa, uint32_t *attr);
292 * core_mmu_va2idx() - Translate from virtual address to table index
293 * @tbl_info: Translation table properties
294 * @va: Virtual address to translate
295 * @returns index in transaltion table
297 static inline unsigned core_mmu_va2idx(struct core_mmu_table_info *tbl_info,
300 return (va - tbl_info->va_base) >> tbl_info->shift;
304 * core_mmu_idx2va() - Translate from table index to virtual address
305 * @tbl_info: Translation table properties
306 * @idx: Index to translate
307 * @returns Virtual address
309 static inline vaddr_t core_mmu_idx2va(struct core_mmu_table_info *tbl_info,
312 return (idx << tbl_info->shift) + tbl_info->va_base;
316 * core_mmu_get_block_offset() - Get offset inside a block/page
317 * @tbl_info: Translation table properties
318 * @pa: Physical address
319 * @returns offset within one block of the translation table
321 static inline size_t core_mmu_get_block_offset(
322 struct core_mmu_table_info *tbl_info, paddr_t pa)
324 return pa & ((1 << tbl_info->shift) - 1);
328 * core_mmu_user_mapping_is_active() - Report if user mapping is active
329 * @returns true if a user VA space is active, false if user VA space is
332 bool core_mmu_user_mapping_is_active(void);
335 * core_mmu_mattr_is_ok() - Check that supplied mem attributes can be used
336 * @returns true if the attributes can be used, false if not.
338 bool core_mmu_mattr_is_ok(uint32_t mattr);
340 void core_mmu_get_mem_by_type(enum teecore_memtypes type, vaddr_t *s,
343 enum teecore_memtypes core_mmu_get_type_by_pa(paddr_t pa);
345 /* Function is deprecated, use virt_to_phys() instead */
346 int core_va2pa_helper(void *va, paddr_t *pa);
348 /* routines to retreive shared mem configuration */
349 bool core_mmu_is_shm_cached(void);
351 bool core_mmu_add_mapping(enum teecore_memtypes type, paddr_t addr, size_t len);
353 /* L1/L2 cache maintenance (op: refer to ???) */
354 unsigned int cache_maintenance_l1(int op, void *va, size_t len);
356 unsigned int cache_maintenance_l2(int op, paddr_t pa, size_t len);
358 static inline unsigned int cache_maintenance_l2(int op __unused,
362 /* Nothing to do about L2 Cache Maintenance when no PL310 */
367 /* various invalidate secure TLB */
368 enum teecore_tlb_op {
369 TLBINV_UNIFIEDTLB, /* invalidate unified tlb */
370 TLBINV_CURRENT_ASID, /* invalidate unified tlb for current ASID */
371 TLBINV_BY_ASID, /* invalidate unified tlb by ASID */
372 TLBINV_BY_MVA, /* invalidate unified tlb by MVA */
375 int core_tlb_maintenance(int op, unsigned int a);
377 /* Cache maintenance operation type */
380 DCACHE_AREA_CLEAN = 0x2,
381 DCACHE_INVALIDATE = 0x3,
382 DCACHE_AREA_INVALIDATE = 0x4,
383 ICACHE_INVALIDATE = 0x5,
384 ICACHE_AREA_INVALIDATE = 0x6,
385 WRITE_BUFFER_DRAIN = 0x7,
386 DCACHE_CLEAN_INV = 0x8,
387 DCACHE_AREA_CLEAN_INV = 0x9,
388 L2CACHE_INVALIDATE = 0xA,
389 L2CACHE_AREA_INVALIDATE = 0xB,
391 L2CACHE_AREA_CLEAN = 0xD,
392 L2CACHE_CLEAN_INV = 0xE,
393 L2CACHE_AREA_CLEAN_INV = 0xF
394 } t_cache_operation_id;
396 /* Check cpu mmu enabled or not */
397 bool cpu_mmu_enabled(void);
399 #endif /* CORE_MMU_H */