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ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5
[platform/kernel/u-boot.git]
/
configs
/
trizepsiv_defconfig
1
CONFIG_ARM=y
2
CONFIG_TARGET_TRIZEPSIV=y
3
# CONFIG_CMD_SETEXPR is not set
projects / platform / kernel / u-boot.git / blob