configs/socfpga_sr1500_defconfig

   1 CONFIG_ARM=y
   2 CONFIG_ARCH_SOCFPGA=y
   3 CONFIG_SYS_MALLOC_LEN=0x4000000
   4 CONFIG_SYS_MEMTEST_START=0x00000000
   5 CONFIG_SYS_MEMTEST_END=0x40000000
   6 CONFIG_ENV_SIZE=0x4000
   7 CONFIG_ENV_OFFSET=0xE0000
   8 CONFIG_ENV_SECT_SIZE=0x10000
   9 CONFIG_DM_GPIO=y
  10 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
  11 CONFIG_SPL_TEXT_BASE=0xFFFF0000
  12 CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
  13 CONFIG_TARGET_SOCFPGA_SR1500=y
  14 CONFIG_ENV_OFFSET_REDUND=0xF0000
  15 CONFIG_DISTRO_DEFAULTS=y
  16 CONFIG_FIT=y
  17 CONFIG_TIMESTAMP=y
  18 # CONFIG_USE_BOOTCOMMAND is not set
  19 CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
  20 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  21 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
  22 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
  23 CONFIG_SYS_CONSOLE_INFO_QUIET=y
  24 # CONFIG_DISPLAY_BOARDINFO is not set
  25 CONFIG_DISPLAY_BOARDINFO_LATE=y
  26 CONFIG_BOARD_EARLY_INIT_F=y
  27 CONFIG_SPL_SPI_LOAD=y
  28 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
  29 CONFIG_CMD_ASKENV=y
  30 CONFIG_CMD_GREPENV=y
  31 CONFIG_CMD_MEMTEST=y
  32 # CONFIG_CMD_FLASH is not set
  33 CONFIG_CMD_GPIO=y
  34 CONFIG_CMD_I2C=y
  35 CONFIG_CMD_MMC=y
  36 CONFIG_CMD_SPI=y
  37 CONFIG_CMD_CACHE=y
  38 CONFIG_CMD_TIME=y
  39 CONFIG_CMD_EXT4_WRITE=y
  40 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
  41 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
  42 CONFIG_CMD_UBI=y
  43 # CONFIG_ISO_PARTITION is not set
  44 # CONFIG_EFI_PARTITION is not set
  45 CONFIG_ENV_IS_IN_SPI_FLASH=y
  46 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
  47 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  48 CONFIG_VERSION_VARIABLE=y
  49 CONFIG_SPL_DM_SEQ_ALIAS=y
  50 CONFIG_BOOTCOUNT_LIMIT=y
  51 CONFIG_DWAPB_GPIO=y
  52 CONFIG_DM_I2C=y
  53 CONFIG_SYS_I2C_DW=y
  54 CONFIG_MMC_DW=y
  55 CONFIG_MTD=y
  56 CONFIG_SF_DEFAULT_SPEED=100000000
  57 CONFIG_SPI_FLASH_STMICRO=y
  58 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  59 CONFIG_SPI_FLASH_MTD=y
  60 CONFIG_PHY_MARVELL=y
  61 CONFIG_DM_ETH=y
  62 CONFIG_PHY_GIGE=y
  63 CONFIG_ETH_DESIGNWARE=y
  64 CONFIG_MII=y
  65 CONFIG_DM_RESET=y
  66 CONFIG_SPI=y
  67 CONFIG_CADENCE_QSPI=y
  68 # CONFIG_SPL_WDT is not set