sandbox: enable CMD_BOOTEFI_HELLO and CMD_EFIDEBUG
[platform/kernel/u-boot.git] / configs / chromebook_speedy_defconfig
1 CONFIG_ARM=y
2 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
3 CONFIG_ARCH_ROCKCHIP=y
4 CONFIG_SYS_TEXT_BASE=0x00100000
5 CONFIG_ROCKCHIP_RK3288=y
6 # CONFIG_SPL_MMC_SUPPORT is not set
7 CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
8 CONFIG_SPL_STACK_R_ADDR=0x80000
9 CONFIG_NR_DRAM_BANKS=1
10 CONFIG_DEBUG_UART_BASE=0xff690000
11 CONFIG_DEBUG_UART_CLOCK=24000000
12 CONFIG_SPL_SPI_FLASH_SUPPORT=y
13 CONFIG_SPL_SPI_SUPPORT=y
14 CONFIG_DEBUG_UART=y
15 CONFIG_SPL_TEXT_BASE=0xff704000
16 CONFIG_USE_PREBOOT=y
17 CONFIG_SILENT_CONSOLE=y
18 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
19 # CONFIG_DISPLAY_CPUINFO is not set
20 CONFIG_DISPLAY_BOARDINFO_LATE=y
21 CONFIG_BOARD_EARLY_INIT_F=y
22 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
23 CONFIG_SPL_STACK_R=y
24 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
25 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
26 # CONFIG_SPL_CRC32_SUPPORT is not set
27 CONFIG_SPL_PAYLOAD="u-boot.img"
28 CONFIG_SPL_SPI_LOAD=y
29 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
30 CONFIG_CMD_GPIO=y
31 CONFIG_CMD_GPT=y
32 CONFIG_CMD_I2C=y
33 CONFIG_CMD_MMC=y
34 CONFIG_CMD_SF_TEST=y
35 CONFIG_CMD_SPI=y
36 CONFIG_CMD_USB=y
37 # CONFIG_CMD_SETEXPR is not set
38 CONFIG_CMD_CACHE=y
39 CONFIG_CMD_TIME=y
40 CONFIG_CMD_PMIC=y
41 CONFIG_CMD_REGULATOR=y
42 # CONFIG_SPL_DOS_PARTITION is not set
43 # CONFIG_SPL_EFI_PARTITION is not set
44 CONFIG_SPL_PARTITION_UUIDS=y
45 CONFIG_SPL_OF_CONTROL=y
46 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
47 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
48 CONFIG_SPL_OF_PLATDATA=y
49 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
50 CONFIG_REGMAP=y
51 CONFIG_SPL_REGMAP=y
52 CONFIG_SYSCON=y
53 CONFIG_SPL_SYSCON=y
54 # CONFIG_SPL_SIMPLE_BUS is not set
55 # CONFIG_SPL_BLK is not set
56 CONFIG_CLK=y
57 CONFIG_SPL_CLK=y
58 CONFIG_ROCKCHIP_GPIO=y
59 CONFIG_I2C_CROS_EC_TUNNEL=y
60 CONFIG_SYS_I2C_ROCKCHIP=y
61 CONFIG_I2C_MUX=y
62 CONFIG_DM_KEYBOARD=y
63 CONFIG_CROS_EC_KEYB=y
64 CONFIG_CROS_EC=y
65 CONFIG_CROS_EC_SPI=y
66 CONFIG_PWRSEQ=y
67 # CONFIG_SPL_DM_MMC is not set
68 CONFIG_MMC_DW=y
69 CONFIG_MMC_DW_ROCKCHIP=y
70 CONFIG_MTD=y
71 CONFIG_SF_DEFAULT_BUS=2
72 CONFIG_SF_DEFAULT_SPEED=20000000
73 CONFIG_SPI_FLASH_GIGADEVICE=y
74 CONFIG_PINCTRL=y
75 CONFIG_PINCONF=y
76 CONFIG_SPL_PINCTRL=y
77 CONFIG_DM_PMIC=y
78 # CONFIG_SPL_PMIC_CHILDREN is not set
79 CONFIG_PMIC_RK8XX=y
80 CONFIG_DM_REGULATOR_FIXED=y
81 CONFIG_REGULATOR_RK8XX=y
82 CONFIG_PWM_ROCKCHIP=y
83 CONFIG_RAM=y
84 CONFIG_SPL_RAM=y
85 CONFIG_DEBUG_UART_SHIFT=2
86 CONFIG_ROCKCHIP_SERIAL=y
87 CONFIG_ROCKCHIP_SPI=y
88 CONFIG_SYSRESET=y
89 CONFIG_USB=y
90 # CONFIG_SPL_DM_USB is not set
91 CONFIG_USB_DWC2=y
92 CONFIG_ROCKCHIP_USB2_PHY=y
93 CONFIG_DM_VIDEO=y
94 # CONFIG_VIDEO_BPP8 is not set
95 CONFIG_CONSOLE_TRUETYPE=y
96 CONFIG_DISPLAY=y
97 CONFIG_VIDEO_ROCKCHIP=y
98 CONFIG_DISPLAY_ROCKCHIP_EDP=y
99 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
100 # CONFIG_USE_PRIVATE_LIBGCC is not set
101 CONFIG_SPL_TINY_MEMSET=y
102 CONFIG_CMD_DHRYSTONE=y
103 CONFIG_ERRNO_STR=y