rockchip: Add basic support for phyCORE-RK3288 SoM based carrier board
[platform/kernel/u-boot.git] / configs / chromebook_minnie_defconfig
1 CONFIG_ARM=y
2 CONFIG_ARCH_ROCKCHIP=y
3 CONFIG_SYS_MALLOC_F_LEN=0x2000
4 CONFIG_ROCKCHIP_RK3288=y
5 # CONFIG_SPL_MMC_SUPPORT is not set
6 CONFIG_TARGET_CHROMEBOOK_MINNIE=y
7 CONFIG_SPL_SPI_FLASH_SUPPORT=y
8 CONFIG_SPL_SPI_SUPPORT=y
9 CONFIG_SPL_STACK_R_ADDR=0x80000
10 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
11 CONFIG_DEBUG_UART=y
12 CONFIG_SILENT_CONSOLE=y
13 # CONFIG_DISPLAY_CPUINFO is not set
14 CONFIG_SPL_STACK_R=y
15 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
16 # CONFIG_CMD_IMLS is not set
17 CONFIG_CMD_GPT=y
18 CONFIG_CMD_MMC=y
19 CONFIG_CMD_SF=y
20 CONFIG_CMD_SPI=y
21 CONFIG_CMD_I2C=y
22 CONFIG_CMD_GPIO=y
23 # CONFIG_CMD_SETEXPR is not set
24 CONFIG_CMD_CACHE=y
25 CONFIG_CMD_TIME=y
26 CONFIG_CMD_PMIC=y
27 CONFIG_CMD_REGULATOR=y
28 # CONFIG_SPL_DOS_PARTITION is not set
29 # CONFIG_SPL_ISO_PARTITION is not set
30 # CONFIG_SPL_EFI_PARTITION is not set
31 CONFIG_SPL_PARTITION_UUIDS=y
32 CONFIG_SPL_OF_CONTROL=y
33 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
34 CONFIG_SPL_OF_PLATDATA=y
35 CONFIG_REGMAP=y
36 CONFIG_SPL_REGMAP=y
37 CONFIG_SYSCON=y
38 CONFIG_SPL_SYSCON=y
39 # CONFIG_SPL_SIMPLE_BUS is not set
40 CONFIG_CLK=y
41 CONFIG_SPL_CLK=y
42 CONFIG_ROCKCHIP_GPIO=y
43 CONFIG_I2C_CROS_EC_TUNNEL=y
44 CONFIG_SYS_I2C_ROCKCHIP=y
45 CONFIG_I2C_MUX=y
46 CONFIG_DM_KEYBOARD=y
47 CONFIG_CROS_EC_KEYB=y
48 CONFIG_CROS_EC=y
49 CONFIG_CROS_EC_SPI=y
50 CONFIG_PWRSEQ=y
51 CONFIG_MMC_DW=y
52 CONFIG_MMC_DW_ROCKCHIP=y
53 CONFIG_PINCTRL=y
54 CONFIG_SPL_PINCTRL=y
55 # CONFIG_SPL_PINCTRL_FULL is not set
56 CONFIG_PINCTRL_ROCKCHIP_RK3288=y
57 CONFIG_DM_PMIC=y
58 # CONFIG_SPL_PMIC_CHILDREN is not set
59 CONFIG_PMIC_RK8XX=y
60 CONFIG_DM_REGULATOR_FIXED=y
61 CONFIG_REGULATOR_RK8XX=y
62 CONFIG_PWM_ROCKCHIP=y
63 CONFIG_RAM=y
64 CONFIG_SPL_RAM=y
65 CONFIG_DEBUG_UART_BASE=0xff690000
66 CONFIG_DEBUG_UART_CLOCK=24000000
67 CONFIG_DEBUG_UART_SHIFT=2
68 CONFIG_SYS_NS16550=y
69 CONFIG_ROCKCHIP_SERIAL=y
70 CONFIG_ROCKCHIP_SPI=y
71 CONFIG_SYSRESET=y
72 CONFIG_DM_VIDEO=y
73 CONFIG_DISPLAY=y
74 CONFIG_VIDEO_ROCKCHIP=y
75 CONFIG_DISPLAY_ROCKCHIP_EDP=y
76 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
77 CONFIG_CONSOLE_SCROLL_LINES=10
78 CONFIG_USE_TINY_PRINTF=y
79 CONFIG_CMD_DHRYSTONE=y
80 CONFIG_ERRNO_STR=y
81 # CONFIG_SPL_OF_LIBFDT is not set