2 * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com
4 * base on universe.h by
6 * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #define PCI_VENDOR PCI_VENDOR_ID_TUNDRA
38 #define PCI_DEVICE PCI_DEVICE_ID_TUNDRA_TSI148
40 typedef struct _TSI148_DEV TSI148_DEV;
49 static TSI148_DEV *dev;
52 * Most of the TSI148 register are BIGENDIAN
53 * This is the reason for the __raw_writel(htonl(x), x) usage!
58 int j, result, lastError = 0;
62 busdevfn = pci_find_device(PCI_VENDOR, PCI_DEVICE, 0);
64 puts("Tsi148: No Tundra Tsi148 found!\n");
68 /* Lets turn Latency off */
69 pci_write_config_dword(busdevfn, 0x0c, 0);
71 dev = malloc(sizeof(*dev));
73 puts("Tsi148: No memory!\n");
78 memset(dev, 0, sizeof(*dev));
79 dev->busdevfn = busdevfn;
81 pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val);
83 dev->uregs = (TSI148 *)val;
85 debug("Tsi148: Base : %p\n", dev->uregs);
88 debug("Tsi148: Read via mapping, PCI_ID = %08X\n", readl(&dev->uregs->pci_id));
89 if (((PCI_DEVICE << 16) | PCI_VENDOR) != readl(&dev->uregs->pci_id)) {
90 printf("Tsi148: Cannot read PCI-ID via Mapping: %08x\n",
91 readl(&dev->uregs->pci_id));
96 debug("Tsi148: PCI_BS = %08X\n", readl(&dev->uregs->pci_mbarl));
98 dev->pci_bs = readl(&dev->uregs->pci_mbarl);
100 /* turn off windows */
101 for (j = 0; j < 8; j++) {
102 __raw_writel(htonl(0x00000000), &dev->uregs->outbound[j].otat);
103 __raw_writel(htonl(0x00000000), &dev->uregs->inbound[j].itat);
106 /* Tsi148 VME timeout etc */
107 __raw_writel(htonl(0x00000084), &dev->uregs->vctrl);
109 if ((__raw_readl(&dev->uregs->vstat) & 0x00000100) != 0)
110 debug("Tsi148: System Controller!\n");
112 debug("Tsi148: Not System Controller!\n");
115 * Lets turn off interrupts
117 /* Disable interrupts in Tsi148 first */
118 __raw_writel(htonl(0x00000000), &dev->uregs->inten);
119 /* Disable interrupt out */
120 __raw_writel(htonl(0x00000000), &dev->uregs->inteo);
122 /* Reset all IRQ's */
123 __raw_writel(htonl(0x03ff3f00), &dev->uregs->intc);
124 /* Map all ints to 0 */
125 __raw_writel(htonl(0x00000000), &dev->uregs->intm1);
126 __raw_writel(htonl(0x00000000), &dev->uregs->intm2);
129 val = __raw_readl(&dev->uregs->vstat);
130 val &= ~(0x00004000);
131 __raw_writel(val, &dev->uregs->vstat);
134 debug("Tsi148: register struct size %08x\n", sizeof(TSI148));
148 * Create pci slave window (access: pci -> vme)
150 int tsi148_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr, int size, int vam, int vdw)
153 unsigned int ctl = 0;
160 for (i = 0; i < 8; i++) {
161 if (0x00000000 == readl(&dev->uregs->outbound[i].otat))
166 printf("Tsi148: No Image available\n");
171 debug("Tsi148: Using image %d\n", i);
173 printf("Tsi148: Pci addr %08x\n", pciAddr);
176 __raw_writel(htonl(pciAddr) , &dev->uregs->outbound[i].otsal);
177 __raw_writel(0x00000000 , &dev->uregs->outbound[i].otsau);
178 __raw_writel(htonl(pciAddr + size), &dev->uregs->outbound[i].oteal);
179 __raw_writel(0x00000000 , &dev->uregs->outbound[i].oteau);
180 __raw_writel(htonl(vmeAddr - pciAddr), &dev->uregs->outbound[i].otofl);
181 __raw_writel(0x00000000 , &dev->uregs->outbound[i].otofu);
183 switch (vam & VME_AM_Axx) {
195 switch (vam & VME_AM_Mxx) {
204 if (vam & VME_AM_SUP)
207 switch (vdw & VME_FLAG_Dxx) {
216 ctl |= 0x80040000; /* enable, no prefetch */
218 __raw_writel(htonl(ctl), &dev->uregs->outbound[i].otat);
220 debug("Tsi148: window-addr =%p\n",
221 &dev->uregs->outbound[i].otsau);
222 debug("Tsi148: pci slave window[%d] attr =%08x\n",
223 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otat)));
224 debug("Tsi148: pci slave window[%d] start =%08x\n",
225 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otsal)));
226 debug("Tsi148: pci slave window[%d] end =%08x\n",
227 i, ntohl(__raw_readl(&dev->uregs->outbound[i].oteal)));
228 debug("Tsi148: pci slave window[%d] offset=%08x\n",
229 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otofl)));
237 unsigned int tsi148_eval_vam(int vam)
239 unsigned int ctl = 0;
241 switch (vam & VME_AM_Axx) {
252 switch (vam & VME_AM_Mxx) {
259 case (VME_AM_PROG | VME_AM_DATA):
264 if (vam & VME_AM_SUP)
266 if (vam & VME_AM_USR)
273 * Create vme slave window (access: vme -> pci)
275 int tsi148_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr, int size, int vam)
278 unsigned int ctl = 0;
285 for (i = 0; i < 8; i++) {
286 if (0x00000000 == readl(&dev->uregs->inbound[i].itat))
291 printf("Tsi148: No Image available\n");
296 debug("Tsi148: Using image %d\n", i);
298 __raw_writel(htonl(vmeAddr), &dev->uregs->inbound[i].itsal);
299 __raw_writel(0x00000000, &dev->uregs->inbound[i].itsau);
300 __raw_writel(htonl(vmeAddr + size), &dev->uregs->inbound[i].iteal);
301 __raw_writel(0x00000000, &dev->uregs->inbound[i].iteau);
302 __raw_writel(htonl(pciAddr - vmeAddr), &dev->uregs->inbound[i].itofl);
303 if (vmeAddr > pciAddr)
304 __raw_writel(0xffffffff, &dev->uregs->inbound[i].itofu);
306 __raw_writel(0x00000000, &dev->uregs->inbound[i].itofu);
308 ctl = tsi148_eval_vam(vam);
309 ctl |= 0x80000000; /* enable */
310 __raw_writel(htonl(ctl), &dev->uregs->inbound[i].itat);
312 debug("Tsi148: window-addr =%p\n",
313 &dev->uregs->inbound[i].itsau);
314 debug("Tsi148: vme slave window[%d] attr =%08x\n",
315 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itat))) ;
316 debug("Tsi148: vme slave window[%d] start =%08x\n",
317 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itsal)));
318 debug("Tsi148: vme slave window[%d] end =%08x\n",
319 i, ntohl(__raw_readl(&dev->uregs->inbound[i].iteal)));
320 debug("Tsi148: vme slave window[%d] offset=%08x\n",
321 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itofl)));
330 * Create vme slave window (access: vme -> gcsr)
332 int tsi148_vme_gcsr_window(unsigned int vmeAddr, int vam)
342 __raw_writel(htonl(vmeAddr), &dev->uregs->gbal);
343 __raw_writel(0x00000000, &dev->uregs->gbau);
345 ctl = tsi148_eval_vam(vam);
346 ctl |= 0x00000080; /* enable */
347 __raw_writel(htonl(ctl), &dev->uregs->gcsrat);
354 * Create vme slave window (access: vme -> crcsr)
356 int tsi148_vme_crcsr_window(unsigned int vmeAddr)
366 __raw_writel(htonl(vmeAddr), &dev->uregs->crol);
367 __raw_writel(0x00000000, &dev->uregs->crou);
369 ctl = 0x00000080; /* enable */
370 __raw_writel(htonl(ctl), &dev->uregs->crat);
378 * Create vme slave window (access: vme -> crg)
380 int tsi148_vme_crg_window(unsigned int vmeAddr, int vam)
390 __raw_writel(htonl(vmeAddr), &dev->uregs->cbal);
391 __raw_writel(0x00000000, &dev->uregs->cbau);
393 ctl = tsi148_eval_vam(vam);
394 ctl |= 0x00000080; /* enable */
395 __raw_writel(htonl(ctl), &dev->uregs->crgat);
402 * Tundra Tsi148 configuration
404 int do_tsi148(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
406 ulong addr1 = 0, addr2 = 0, size = 0, vam = 0, vdw = 0;
413 addr1 = simple_strtoul(argv[2], NULL, 16);
415 addr2 = simple_strtoul(argv[3], NULL, 16);
417 size = simple_strtoul(argv[4], NULL, 16);
419 vam = simple_strtoul(argv[5], NULL, 16);
421 vdw = simple_strtoul(argv[7], NULL, 16);
425 if (strcmp(argv[1], "crg") == 0) {
427 printf("Tsi148: Configuring VME CRG Window (VME->CRG):\n");
428 printf(" vme=%08lx vam=%02lx\n", addr1, vam);
429 tsi148_vme_crg_window(addr1, vam);
431 printf("Tsi148: Configuring VME CR/CSR Window (VME->CR/CSR):\n");
432 printf(" pci=%08lx\n", addr1);
433 tsi148_vme_crcsr_window(addr1);
441 printf("Tsi148: Configuring VME GCSR Window (VME->GCSR):\n");
442 printf(" vme=%08lx vam=%02lx\n", addr1, vam);
443 tsi148_vme_gcsr_window(addr1, vam);
446 printf("Tsi148: Configuring VME Slave Window (VME->PCI):\n");
447 printf(" vme=%08lx pci=%08lx size=%08lx vam=%02lx\n",
448 addr1, addr2, size, vam);
449 tsi148_vme_slave_window(addr1, addr2, size, vam);
452 printf("Tsi148: Configuring PCI Slave Window (PCI->VME):\n");
453 printf(" pci=%08lx vme=%08lx size=%08lx vam=%02lx vdw=%02lx\n",
454 addr1, addr2, size, vam, vdw);
455 tsi148_pci_slave_window(addr1, addr2, size, vam, vdw);
458 printf("Tsi148: Command %s not supported!\n", argv[1]);
465 tsi148, 8, 1, do_tsi148,
466 "tsi148 - initialize and configure Turndra Tsi148\n",
468 " - initialize tsi148\n"
469 "tsi148 vme [vme_addr] [pci_addr] [size] [vam]\n"
470 " - create vme slave window (access: vme->pci)\n"
471 "tsi148 pci [pci_addr] [vme_addr] [size] [vam] [vdw]\n"
472 " - create pci slave window (access: pci->vme)\n"
473 "tsi148 crg [vme_addr] [vam]\n"
474 " - create vme slave window: (access vme->CRG\n"
475 "tsi148 crcsr [pci_addr]\n"
476 " - create vme slave window: (access vme->CR/CSR\n"
477 "tsi148 gcsr [vme_addr] [vam]\n"
478 " - create vme slave window: (access vme->GCSR\n"
479 " [vam] = VMEbus Address-Modifier: 01 -> A16 Address Space\n"
480 " 02 -> A24 Address Space\n"
481 " 03 -> A32 Address Space\n"
482 " 04 -> Usr AM Code\n"
483 " 08 -> Supervisor AM Code\n"
484 " 10 -> Data AM Code\n"
485 " 20 -> Program AM Code\n"
486 " [vdw] = VMEbus Maximum Datawidth: 02 -> D16 Data Width\n"
487 " 03 -> D32 Data Width\n"