1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
18 #include <env_internal.h>
33 #include <status_led.h>
39 #ifdef CONFIG_MACH_TYPE
40 #include <asm/mach-types.h>
42 #if defined(CONFIG_MP) && defined(CONFIG_PPC)
46 #include <asm/sections.h>
48 #include <linux/errno.h>
51 * Pointer to initial global data area
53 * Here we initialize it if needed.
55 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
56 #undef XTRN_DECLARE_GLOBAL_DATA_PTR
57 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
58 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
60 DECLARE_GLOBAL_DATA_PTR;
64 * TODO(sjg@chromium.org): IMO this code should be
65 * refactored to a single function, something like:
67 * void led_set_state(enum led_colour_t colour, int on);
69 /************************************************************************
70 * Coloured LED functionality
71 ************************************************************************
72 * May be supplied by boards if desired
74 __weak void coloured_LED_init(void) {}
75 __weak void red_led_on(void) {}
76 __weak void red_led_off(void) {}
77 __weak void green_led_on(void) {}
78 __weak void green_led_off(void) {}
79 __weak void yellow_led_on(void) {}
80 __weak void yellow_led_off(void) {}
81 __weak void blue_led_on(void) {}
82 __weak void blue_led_off(void) {}
85 * Why is gd allocated a register? Prior to reloc it might be better to
86 * just pass it around to each function in this file?
88 * After reloc one could argue that it is hardly used and doesn't need
89 * to be in a register. Or if it is it should perhaps hold pointers to all
90 * global data for all modules, so that post-reloc we can avoid the massive
91 * literal pool we get on ARM. Or perhaps just encourage each module to use
95 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
96 static int init_func_watchdog_init(void)
98 # if defined(CONFIG_HW_WATCHDOG) && \
99 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
100 defined(CONFIG_SH) || \
101 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
102 defined(CONFIG_IMX_WATCHDOG))
104 puts(" Watchdog enabled\n");
111 int init_func_watchdog_reset(void)
117 #endif /* CONFIG_WATCHDOG */
119 __weak void board_add_ram_info(int use_default)
121 /* please define platform specific board_add_ram_info() */
124 static int init_baud_rate(void)
126 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
130 static int display_text_info(void)
132 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
133 ulong bss_start, bss_end, text_base;
135 bss_start = (ulong)&__bss_start;
136 bss_end = (ulong)&__bss_end;
138 #ifdef CONFIG_SYS_TEXT_BASE
139 text_base = CONFIG_SYS_TEXT_BASE;
141 text_base = CONFIG_SYS_MONITOR_BASE;
144 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
145 text_base, bss_start, bss_end);
151 #ifdef CONFIG_SYSRESET
152 static int print_resetinfo(void)
158 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
160 debug("%s: No sysreset device found (error: %d)\n",
162 /* Not all boards have sysreset drivers available during early
163 * boot, so don't fail if one can't be found.
168 if (!sysreset_get_status(dev, status, sizeof(status)))
169 printf("%s", status);
175 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
176 static int print_cpuinfo(void)
182 ret = uclass_first_device_err(UCLASS_CPU, &dev);
184 debug("%s: Could not get CPU device (err = %d)\n",
189 ret = cpu_get_desc(dev, desc, sizeof(desc));
191 debug("%s: Could not get CPU description (err = %d)\n",
196 printf("CPU: %s\n", desc);
202 static int announce_dram_init(void)
208 static int show_dram_config(void)
210 unsigned long long size;
212 #ifdef CONFIG_NR_DRAM_BANKS
215 debug("\nRAM Configuration:\n");
216 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
217 size += gd->bd->bi_dram[i].size;
218 debug("Bank #%d: %llx ", i,
219 (unsigned long long)(gd->bd->bi_dram[i].start));
221 print_size(gd->bd->bi_dram[i].size, "\n");
229 print_size(size, "");
230 board_add_ram_info(0);
236 __weak int dram_init_banksize(void)
238 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
239 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
240 gd->bd->bi_dram[0].size = get_effective_memsize();
246 #if defined(CONFIG_SYS_I2C)
247 static int init_func_i2c(void)
250 #ifdef CONFIG_SYS_I2C
253 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
260 #if defined(CONFIG_VID)
261 __weak int init_func_vid(void)
267 static int setup_mon_len(void)
269 #if defined(__ARM__) || defined(__MICROBLAZE__)
270 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
271 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
272 gd->mon_len = (ulong)&_end - (ulong)_init;
273 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
274 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
275 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
276 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
277 #elif defined(CONFIG_SYS_MONITOR_BASE)
278 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
279 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
284 static int setup_spl_handoff(void)
286 #if CONFIG_IS_ENABLED(HANDOFF)
287 gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
288 sizeof(struct spl_handoff));
289 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
295 __weak int arch_cpu_init(void)
300 __weak int mach_cpu_init(void)
305 /* Get the top of usable RAM */
306 __weak ulong board_get_usable_ram_top(ulong total_size)
308 #ifdef CONFIG_SYS_SDRAM_BASE
310 * Detect whether we have so much RAM that it goes past the end of our
311 * 32-bit address space. If so, clip the usable RAM so it doesn't.
313 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
315 * Will wrap back to top of 32-bit space when reservations
323 static int setup_dest_addr(void)
325 debug("Monitor len: %08lX\n", gd->mon_len);
327 * Ram is setup, size stored in gd !!
329 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
330 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
332 * Subtract specified amount of memory to hide so that it won't
333 * get "touched" at all by U-Boot. By fixing up gd->ram_size
334 * the Linux kernel should now get passed the now "corrected"
335 * memory size and won't touch it either. This should work
336 * for arch/ppc and arch/powerpc. Only Linux board ports in
337 * arch/powerpc with bootwrapper support, that recalculate the
338 * memory size from the SDRAM controller setup will have to
341 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
343 #ifdef CONFIG_SYS_SDRAM_BASE
344 gd->ram_base = CONFIG_SYS_SDRAM_BASE;
346 gd->ram_top = gd->ram_base + get_effective_memsize();
347 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
348 gd->relocaddr = gd->ram_top;
349 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
350 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
352 * We need to make sure the location we intend to put secondary core
353 * boot code is reserved and not used by any part of u-boot
355 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
356 gd->relocaddr = determine_mp_bootpg(NULL);
357 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
364 /* reserve protected RAM */
365 static int reserve_pram(void)
369 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
370 gd->relocaddr -= (reg << 10); /* size is in kB */
371 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
375 #endif /* CONFIG_PRAM */
377 /* Round memory pointer down to next 4 kB limit */
378 static int reserve_round_4k(void)
380 gd->relocaddr &= ~(4096 - 1);
385 __weak int reserve_mmu(void)
387 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
388 /* reserve TLB table */
389 gd->arch.tlb_size = PGTABLE_SIZE;
390 gd->relocaddr -= gd->arch.tlb_size;
392 /* round down to next 64 kB limit */
393 gd->relocaddr &= ~(0x10000 - 1);
395 gd->arch.tlb_addr = gd->relocaddr;
396 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
397 gd->arch.tlb_addr + gd->arch.tlb_size);
399 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
401 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
402 * with location within secure ram.
404 gd->arch.tlb_allocated = gd->arch.tlb_addr;
412 static int reserve_video(void)
414 #ifdef CONFIG_DM_VIDEO
418 addr = gd->relocaddr;
419 ret = video_reserve(&addr);
422 gd->relocaddr = addr;
423 #elif defined(CONFIG_LCD)
424 # ifdef CONFIG_FB_ADDR
425 gd->fb_base = CONFIG_FB_ADDR;
427 /* reserve memory for LCD display (always full pages) */
428 gd->relocaddr = lcd_setmem(gd->relocaddr);
429 gd->fb_base = gd->relocaddr;
430 # endif /* CONFIG_FB_ADDR */
436 static int reserve_trace(void)
439 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
440 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
441 debug("Reserving %luk for trace data at: %08lx\n",
442 (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
448 static int reserve_uboot(void)
450 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
452 * reserve memory for U-Boot code, data & bss
453 * round down to next 4 kB limit
455 gd->relocaddr -= gd->mon_len;
456 gd->relocaddr &= ~(4096 - 1);
457 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
458 /* round down to next 64 kB limit so that IVPR stays aligned */
459 gd->relocaddr &= ~(65536 - 1);
462 debug("Reserving %ldk for U-Boot at: %08lx\n",
463 gd->mon_len >> 10, gd->relocaddr);
466 gd->start_addr_sp = gd->relocaddr;
471 #ifdef CONFIG_SYS_NONCACHED_MEMORY
472 static int reserve_noncached(void)
475 * The value of gd->start_addr_sp must match the value of malloc_start
476 * calculated in boatrd_f.c:initr_malloc(), which is passed to
477 * board_r.c:mem_malloc_init() and then used by
478 * cache.c:noncached_init()
480 * These calculations must match the code in cache.c:noncached_init()
482 gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
484 gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
486 debug("Reserving %dM for noncached_alloc() at: %08lx\n",
487 CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
493 /* reserve memory for malloc() area */
494 static int reserve_malloc(void)
496 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
497 debug("Reserving %dk for malloc() at: %08lx\n",
498 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
499 #ifdef CONFIG_SYS_NONCACHED_MEMORY
506 /* (permanently) allocate a Board Info struct */
507 static int reserve_board(void)
510 gd->start_addr_sp -= sizeof(bd_t);
511 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
512 memset(gd->bd, '\0', sizeof(bd_t));
513 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
514 sizeof(bd_t), gd->start_addr_sp);
519 static int setup_machine(void)
521 #ifdef CONFIG_MACH_TYPE
522 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
527 static int reserve_global_data(void)
529 gd->start_addr_sp -= sizeof(gd_t);
530 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
531 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
532 sizeof(gd_t), gd->start_addr_sp);
536 static int reserve_fdt(void)
538 #ifndef CONFIG_OF_EMBED
540 * If the device tree is sitting immediately above our image then we
541 * must relocate it. If it is embedded in the data section, then it
542 * will be relocated with other data.
545 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
547 gd->start_addr_sp -= gd->fdt_size;
548 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
549 debug("Reserving %lu Bytes for FDT at: %08lx\n",
550 gd->fdt_size, gd->start_addr_sp);
557 static int reserve_bootstage(void)
559 #ifdef CONFIG_BOOTSTAGE
560 int size = bootstage_get_size();
562 gd->start_addr_sp -= size;
563 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
564 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
571 __weak int arch_reserve_stacks(void)
576 static int reserve_stacks(void)
578 /* make stack pointer 16-byte aligned */
579 gd->start_addr_sp -= 16;
580 gd->start_addr_sp &= ~0xf;
583 * let the architecture-specific code tailor gd->start_addr_sp and
586 return arch_reserve_stacks();
589 static int reserve_bloblist(void)
591 #ifdef CONFIG_BLOBLIST
592 gd->start_addr_sp &= ~0xf;
593 gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE;
594 gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
600 static int display_new_sp(void)
602 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
607 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
609 static int setup_board_part1(void)
614 * Save local variables to board info struct
616 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
617 bd->bi_memsize = gd->ram_size; /* size in bytes */
619 #ifdef CONFIG_SYS_SRAM_BASE
620 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
621 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
624 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
625 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
627 #if defined(CONFIG_M68K)
628 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
630 #if defined(CONFIG_MPC83xx)
631 bd->bi_immrbar = CONFIG_SYS_IMMR;
638 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
639 static int setup_board_part2(void)
643 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
644 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
645 #if defined(CONFIG_CPM2)
646 bd->bi_cpmfreq = gd->arch.cpm_clk;
647 bd->bi_brgfreq = gd->arch.brg_clk;
648 bd->bi_sccfreq = gd->arch.scc_clk;
649 bd->bi_vco = gd->arch.vco_out;
650 #endif /* CONFIG_CPM2 */
651 #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
652 bd->bi_pcifreq = gd->pci_clk;
654 #if defined(CONFIG_EXTRA_CLOCK)
655 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
656 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
657 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
665 static int init_post(void)
667 post_bootmode_init();
668 post_run(NULL, POST_ROM | post_bootmode_get(0));
674 static int reloc_fdt(void)
676 #ifndef CONFIG_OF_EMBED
677 if (gd->flags & GD_FLG_SKIP_RELOC)
680 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
681 gd->fdt_blob = gd->new_fdt;
688 static int reloc_bootstage(void)
690 #ifdef CONFIG_BOOTSTAGE
691 if (gd->flags & GD_FLG_SKIP_RELOC)
693 if (gd->new_bootstage) {
694 int size = bootstage_get_size();
696 debug("Copying bootstage from %p to %p, size %x\n",
697 gd->bootstage, gd->new_bootstage, size);
698 memcpy(gd->new_bootstage, gd->bootstage, size);
699 gd->bootstage = gd->new_bootstage;
700 bootstage_relocate();
707 static int reloc_bloblist(void)
709 #ifdef CONFIG_BLOBLIST
710 if (gd->flags & GD_FLG_SKIP_RELOC)
712 if (gd->new_bloblist) {
713 int size = CONFIG_BLOBLIST_SIZE;
715 debug("Copying bloblist from %p to %p, size %x\n",
716 gd->bloblist, gd->new_bloblist, size);
717 memcpy(gd->new_bloblist, gd->bloblist, size);
718 gd->bloblist = gd->new_bloblist;
725 static int setup_reloc(void)
727 if (gd->flags & GD_FLG_SKIP_RELOC) {
728 debug("Skipping relocation due to flag\n");
732 #ifdef CONFIG_SYS_TEXT_BASE
734 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
735 #elif defined(CONFIG_M68K)
737 * On all ColdFire arch cpu, monitor code starts always
738 * just after the default vector table location, so at 0x400
740 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
741 #elif !defined(CONFIG_SANDBOX)
742 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
745 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
747 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
748 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
749 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
755 #ifdef CONFIG_OF_BOARD_FIXUP
756 static int fix_fdt(void)
758 return board_fix_fdt((void *)gd->fdt_blob);
762 /* ARM calls relocate_code from its crt0.S */
763 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
764 !CONFIG_IS_ENABLED(X86_64)
766 static int jump_to_copy(void)
768 if (gd->flags & GD_FLG_SKIP_RELOC)
771 * x86 is special, but in a nice way. It uses a trampoline which
772 * enables the dcache if possible.
774 * For now, other archs use relocate_code(), which is implemented
775 * similarly for all archs. When we do generic relocation, hopefully
776 * we can make all archs enable the dcache prior to relocation.
778 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
780 * SDRAM and console are now initialised. The final stack can now
781 * be setup in SDRAM. Code execution will continue in Flash, but
782 * with the stack in SDRAM and Global Data in temporary memory
785 arch_setup_gd(gd->new_gd);
786 board_init_f_r_trampoline(gd->start_addr_sp);
788 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
795 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
796 static int initf_bootstage(void)
798 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
799 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
802 ret = bootstage_init(!from_spl);
806 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
807 CONFIG_BOOTSTAGE_STASH_SIZE);
809 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
810 if (ret && ret != -ENOENT) {
811 debug("Failed to unstash bootstage: err=%d\n", ret);
816 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
821 static int initf_console_record(void)
823 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
824 return console_record_init();
830 static int initf_dm(void)
832 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
835 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
836 ret = dm_init_and_scan(true);
837 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
841 #ifdef CONFIG_TIMER_EARLY
842 ret = dm_timer_init();
850 /* Architecture-specific memory reservation */
851 __weak int reserve_arch(void)
856 __weak int arch_cpu_init_dm(void)
861 static const init_fnc_t init_sequence_f[] = {
863 #ifdef CONFIG_OF_CONTROL
866 #ifdef CONFIG_TRACE_EARLY
871 initf_bootstage, /* uses its own timer, so does not need DM */
872 #ifdef CONFIG_BLOBLIST
876 initf_console_record,
877 #if defined(CONFIG_HAVE_FSP)
880 arch_cpu_init, /* basic arch cpu dependent setup */
881 mach_cpu_init, /* SoC/machine dependent CPU setup */
884 #if defined(CONFIG_BOARD_EARLY_INIT_F)
887 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
888 /* get CPU and bus clocks according to the environment variable */
889 get_clocks, /* get CPU and bus clocks (etc.) */
891 #if !defined(CONFIG_M68K)
892 timer_init, /* initialize timer */
894 #if defined(CONFIG_BOARD_POSTCLK_INIT)
897 env_init, /* initialize environment */
898 init_baud_rate, /* initialze baudrate settings */
899 serial_init, /* serial communications setup */
900 console_init_f, /* stage 1 init of console */
901 display_options, /* say that we are here */
902 display_text_info, /* show debugging info if required */
903 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
906 #if defined(CONFIG_SYSRESET)
909 #if defined(CONFIG_DISPLAY_CPUINFO)
910 print_cpuinfo, /* display cpu info (and speed) */
912 #if defined(CONFIG_DTB_RESELECT)
915 #if defined(CONFIG_DISPLAY_BOARDINFO)
918 INIT_FUNC_WATCHDOG_INIT
919 #if defined(CONFIG_MISC_INIT_F)
922 INIT_FUNC_WATCHDOG_RESET
923 #if defined(CONFIG_SYS_I2C)
926 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
930 dram_init, /* configure available RAM banks */
934 INIT_FUNC_WATCHDOG_RESET
935 #if defined(CONFIG_SYS_DRAM_TEST)
937 #endif /* CONFIG_SYS_DRAM_TEST */
938 INIT_FUNC_WATCHDOG_RESET
943 INIT_FUNC_WATCHDOG_RESET
945 * Now that we have DRAM mapped and working, we can
946 * relocate the code and continue running from DRAM.
948 * Reserve memory at end of RAM for (top down in that order):
949 * - area that won't get touched by U-Boot and Linux (optional)
950 * - kernel log buffer
954 * - board info struct
978 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
982 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
983 INIT_FUNC_WATCHDOG_RESET
987 #ifdef CONFIG_OF_BOARD_FIXUP
990 INIT_FUNC_WATCHDOG_RESET
995 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
1000 #if defined(CONFIG_XTENSA)
1003 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
1004 !CONFIG_IS_ENABLED(X86_64)
1010 void board_init_f(ulong boot_flags)
1012 gd->flags = boot_flags;
1013 gd->have_console = 0;
1015 if (initcall_run_list(init_sequence_f))
1018 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
1019 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
1020 !defined(CONFIG_ARC)
1021 /* NOTREACHED - jump_to_copy() does not return */
1026 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
1028 * For now this code is only used on x86.
1030 * init_sequence_f_r is the list of init functions which are run when
1031 * U-Boot is executing from Flash with a semi-limited 'C' environment.
1032 * The following limitations must be considered when implementing an
1034 * - 'static' variables are read-only
1035 * - Global Data (gd->xxx) is read/write
1037 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1038 * supported). It _should_, if possible, copy global data to RAM and
1039 * initialise the CPU caches (to speed up the relocation process)
1041 * NOTE: At present only x86 uses this route, but it is intended that
1042 * all archs will move to this when generic relocation is implemented.
1044 static const init_fnc_t init_sequence_f_r[] = {
1045 #if !CONFIG_IS_ENABLED(X86_64)
1052 void board_init_f_r(void)
1054 if (initcall_run_list(init_sequence_f_r))
1058 * The pre-relocation drivers may be using memory that has now gone
1059 * away. Mark serial as unavailable - this will fall back to the debug
1060 * UART if available.
1062 * Do the same with log drivers since the memory may not be available.
1064 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
1070 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1071 * Transfer execution from Flash to RAM by calculating the address
1072 * of the in-RAM copy of board_init_r() and calling it
1074 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
1076 /* NOTREACHED - board_init_r() does not return */
1079 #endif /* CONFIG_X86 */