1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
14 #include <bootstage.h>
15 #include <clock_legacy.h>
20 #include <display_options.h>
23 #include <env_internal.h>
42 #include <status_led.h>
48 #include <asm/cache.h>
49 #if defined(CONFIG_MP) && defined(CONFIG_PPC)
52 #include <asm/global_data.h>
54 #include <asm/sections.h>
56 #include <linux/errno.h>
57 #include <linux/log2.h>
59 DECLARE_GLOBAL_DATA_PTR;
62 * TODO(sjg@chromium.org): IMO this code should be
63 * refactored to a single function, something like:
65 * void led_set_state(enum led_colour_t colour, int on);
67 /************************************************************************
68 * Coloured LED functionality
69 ************************************************************************
70 * May be supplied by boards if desired
72 __weak void coloured_LED_init(void) {}
73 __weak void red_led_on(void) {}
74 __weak void red_led_off(void) {}
75 __weak void green_led_on(void) {}
76 __weak void green_led_off(void) {}
77 __weak void yellow_led_on(void) {}
78 __weak void yellow_led_off(void) {}
79 __weak void blue_led_on(void) {}
80 __weak void blue_led_off(void) {}
83 * Why is gd allocated a register? Prior to reloc it might be better to
84 * just pass it around to each function in this file?
86 * After reloc one could argue that it is hardly used and doesn't need
87 * to be in a register. Or if it is it should perhaps hold pointers to all
88 * global data for all modules, so that post-reloc we can avoid the massive
89 * literal pool we get on ARM. Or perhaps just encourage each module to use
93 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
94 static int init_func_watchdog_init(void)
96 # if defined(CONFIG_HW_WATCHDOG) && \
97 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
98 defined(CONFIG_SH) || \
99 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
100 defined(CONFIG_IMX_WATCHDOG))
102 puts(" Watchdog enabled\n");
109 int init_func_watchdog_reset(void)
115 #endif /* CONFIG_WATCHDOG */
117 __weak void board_add_ram_info(int use_default)
119 /* please define platform specific board_add_ram_info() */
122 static int init_baud_rate(void)
124 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
128 static int display_text_info(void)
130 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
131 ulong bss_start, bss_end, text_base;
133 bss_start = (ulong)&__bss_start;
134 bss_end = (ulong)&__bss_end;
136 #ifdef CONFIG_SYS_TEXT_BASE
137 text_base = CONFIG_SYS_TEXT_BASE;
139 text_base = CONFIG_SYS_MONITOR_BASE;
142 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
143 text_base, bss_start, bss_end);
149 #ifdef CONFIG_SYSRESET
150 static int print_resetinfo(void)
156 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
158 debug("%s: No sysreset device found (error: %d)\n",
160 /* Not all boards have sysreset drivers available during early
161 * boot, so don't fail if one can't be found.
166 if (!sysreset_get_status(dev, status, sizeof(status)))
167 printf("%s", status);
173 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
174 static int print_cpuinfo(void)
180 dev = cpu_get_current_dev();
182 debug("%s: Could not get CPU device\n",
187 ret = cpu_get_desc(dev, desc, sizeof(desc));
189 debug("%s: Could not get CPU description (err = %d)\n",
194 printf("CPU: %s\n", desc);
200 static int announce_dram_init(void)
207 * From input size calculate its nearest rounded unit scale (multiply of 2^10)
208 * and value in calculated unit scale multiplied by 10 (as fractional fixed
209 * point number with one decimal digit), which is human natural format,
210 * same what uses print_size() function for displaying. Mathematically it is:
211 * round_nearest(val * 2^scale) = size * 10; where: 10 <= val < 10240.
213 * For example for size=87654321 we calculate scale=20 and val=836 which means
214 * that input has natural human format 83.6 M (mega = 2^20).
216 #define compute_size_scale_val(size, scale, val) do { \
217 scale = ilog2(size) / 10 * 10; \
218 val = (10 * size + ((1ULL << scale) >> 1)) >> scale; \
219 if (val == 10240) { val = 10; scale += 10; } \
223 * Check if the sizes in their natural units written in decimal format with
224 * one fraction number are same.
226 static int sizes_near(unsigned long long size1, unsigned long long size2)
228 unsigned int size1_scale, size1_val, size2_scale, size2_val;
230 compute_size_scale_val(size1, size1_scale, size1_val);
231 compute_size_scale_val(size2, size2_scale, size2_val);
233 return size1_scale == size2_scale && size1_val == size2_val;
236 static int show_dram_config(void)
238 unsigned long long size;
241 debug("\nRAM Configuration:\n");
242 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
243 size += gd->bd->bi_dram[i].size;
244 debug("Bank #%d: %llx ", i,
245 (unsigned long long)(gd->bd->bi_dram[i].start));
247 print_size(gd->bd->bi_dram[i].size, "\n");
252 print_size(gd->ram_size, "");
253 if (!sizes_near(gd->ram_size, size)) {
254 printf(" (effective ");
255 print_size(size, ")");
257 board_add_ram_info(0);
263 __weak int dram_init_banksize(void)
265 gd->bd->bi_dram[0].start = gd->ram_base;
266 gd->bd->bi_dram[0].size = get_effective_memsize();
271 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
272 static int init_func_i2c(void)
281 #if defined(CONFIG_VID)
282 __weak int init_func_vid(void)
288 static int setup_mon_len(void)
290 #if defined(__ARM__) || defined(__MICROBLAZE__)
291 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
292 #elif defined(CONFIG_SANDBOX)
294 #elif defined(CONFIG_EFI_APP)
295 gd->mon_len = (ulong)&_end - (ulong)_init;
296 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
297 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
298 #elif defined(CONFIG_SH) || defined(CONFIG_RISCV)
299 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
300 #elif defined(CONFIG_SYS_MONITOR_BASE)
301 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
302 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
307 static int setup_spl_handoff(void)
309 #if CONFIG_IS_ENABLED(HANDOFF)
310 gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
311 sizeof(struct spl_handoff));
312 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
318 __weak int arch_cpu_init(void)
323 __weak int mach_cpu_init(void)
328 /* Get the top of usable RAM */
329 __weak phys_size_t board_get_usable_ram_top(phys_size_t total_size)
331 #if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0
333 * Detect whether we have so much RAM that it goes past the end of our
334 * 32-bit address space. If so, clip the usable RAM so it doesn't.
336 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
338 * Will wrap back to top of 32-bit space when reservations
346 static int setup_dest_addr(void)
348 debug("Monitor len: %08lX\n", gd->mon_len);
350 * Ram is setup, size stored in gd !!
352 debug("Ram size: %08llX\n", (unsigned long long)gd->ram_size);
353 #if CONFIG_VAL(SYS_MEM_TOP_HIDE)
355 * Subtract specified amount of memory to hide so that it won't
356 * get "touched" at all by U-Boot. By fixing up gd->ram_size
357 * the Linux kernel should now get passed the now "corrected"
358 * memory size and won't touch it either. This should work
359 * for arch/ppc and arch/powerpc. Only Linux board ports in
360 * arch/powerpc with bootwrapper support, that recalculate the
361 * memory size from the SDRAM controller setup will have to
364 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
366 #ifdef CONFIG_SYS_SDRAM_BASE
367 gd->ram_base = CONFIG_SYS_SDRAM_BASE;
369 gd->ram_top = gd->ram_base + get_effective_memsize();
370 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
371 gd->relocaddr = gd->ram_top;
372 debug("Ram top: %08llX\n", (unsigned long long)gd->ram_top);
373 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
375 * We need to make sure the location we intend to put secondary core
376 * boot code is reserved and not used by any part of u-boot
378 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
379 gd->relocaddr = determine_mp_bootpg(NULL);
380 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
387 /* reserve protected RAM */
388 static int reserve_pram(void)
392 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
393 gd->relocaddr -= (reg << 10); /* size is in kB */
394 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
398 #endif /* CONFIG_PRAM */
400 /* Round memory pointer down to next 4 kB limit */
401 static int reserve_round_4k(void)
403 gd->relocaddr &= ~(4096 - 1);
407 __weak int arch_reserve_mmu(void)
412 static int reserve_video(void)
414 #ifdef CONFIG_DM_VIDEO
418 addr = gd->relocaddr;
419 ret = video_reserve(&addr);
422 debug("Reserving %luk for video at: %08lx\n",
423 ((unsigned long)gd->relocaddr - addr) >> 10, addr);
424 gd->relocaddr = addr;
425 #elif defined(CONFIG_LCD)
426 /* reserve memory for LCD display (always full pages) */
427 gd->relocaddr = lcd_setmem(gd->relocaddr);
428 gd->fb_base = gd->relocaddr;
434 static int reserve_trace(void)
437 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
438 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
439 debug("Reserving %luk for trace data at: %08lx\n",
440 (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
446 static int reserve_uboot(void)
448 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
450 * reserve memory for U-Boot code, data & bss
451 * round down to next 4 kB limit
453 gd->relocaddr -= gd->mon_len;
454 gd->relocaddr &= ~(4096 - 1);
455 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
456 /* round down to next 64 kB limit so that IVPR stays aligned */
457 gd->relocaddr &= ~(65536 - 1);
460 debug("Reserving %ldk for U-Boot at: %08lx\n",
461 gd->mon_len >> 10, gd->relocaddr);
464 gd->start_addr_sp = gd->relocaddr;
470 * reserve after start_addr_sp the requested size and make the stack pointer
471 * 16-byte aligned, this alignment is needed for cast on the reserved memory
472 * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
473 * = ARMv8 Instruction Set Overview: quad word, 16 bytes
475 static unsigned long reserve_stack_aligned(size_t size)
477 return ALIGN_DOWN(gd->start_addr_sp - size, 16);
480 #ifdef CONFIG_SYS_NONCACHED_MEMORY
481 static int reserve_noncached(void)
484 * The value of gd->start_addr_sp must match the value of malloc_start
485 * calculated in boatrd_f.c:initr_malloc(), which is passed to
486 * board_r.c:mem_malloc_init() and then used by
487 * cache.c:noncached_init()
489 * These calculations must match the code in cache.c:noncached_init()
491 gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
493 gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
495 debug("Reserving %dM for noncached_alloc() at: %08lx\n",
496 CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
502 /* reserve memory for malloc() area */
503 static int reserve_malloc(void)
505 gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN);
506 debug("Reserving %dk for malloc() at: %08lx\n",
507 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
508 #ifdef CONFIG_SYS_NONCACHED_MEMORY
515 /* (permanently) allocate a Board Info struct */
516 static int reserve_board(void)
519 gd->start_addr_sp = reserve_stack_aligned(sizeof(struct bd_info));
520 gd->bd = (struct bd_info *)map_sysmem(gd->start_addr_sp,
521 sizeof(struct bd_info));
522 memset(gd->bd, '\0', sizeof(struct bd_info));
523 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
524 sizeof(struct bd_info), gd->start_addr_sp);
529 static int reserve_global_data(void)
531 gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t));
532 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
533 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
534 sizeof(gd_t), gd->start_addr_sp);
538 static int reserve_fdt(void)
540 if (!IS_ENABLED(CONFIG_OF_EMBED)) {
542 * If the device tree is sitting immediately above our image
543 * then we must relocate it. If it is embedded in the data
544 * section, then it will be relocated with other data.
547 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32);
549 gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
550 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
551 debug("Reserving %lu Bytes for FDT at: %08lx\n",
552 gd->fdt_size, gd->start_addr_sp);
559 static int reserve_bootstage(void)
561 #ifdef CONFIG_BOOTSTAGE
562 int size = bootstage_get_size();
564 gd->start_addr_sp = reserve_stack_aligned(size);
565 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
566 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
573 __weak int arch_reserve_stacks(void)
578 static int reserve_stacks(void)
580 /* make stack pointer 16-byte aligned */
581 gd->start_addr_sp = reserve_stack_aligned(16);
584 * let the architecture-specific code tailor gd->start_addr_sp and
587 return arch_reserve_stacks();
590 static int reserve_bloblist(void)
592 #ifdef CONFIG_BLOBLIST
593 /* Align to a 4KB boundary for easier reading of addresses */
594 gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp -
595 CONFIG_BLOBLIST_SIZE_RELOC, 0x1000);
596 gd->new_bloblist = map_sysmem(gd->start_addr_sp,
597 CONFIG_BLOBLIST_SIZE_RELOC);
603 static int display_new_sp(void)
605 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
610 __weak int arch_setup_bdinfo(void)
615 int setup_bdinfo(void)
617 struct bd_info *bd = gd->bd;
619 if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) {
620 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
621 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
624 return arch_setup_bdinfo();
628 static int init_post(void)
630 post_bootmode_init();
631 post_run(NULL, POST_ROM | post_bootmode_get(0));
637 static int reloc_fdt(void)
639 if (!IS_ENABLED(CONFIG_OF_EMBED)) {
640 if (gd->flags & GD_FLG_SKIP_RELOC)
643 memcpy(gd->new_fdt, gd->fdt_blob,
644 fdt_totalsize(gd->fdt_blob));
645 gd->fdt_blob = gd->new_fdt;
652 static int reloc_bootstage(void)
654 #ifdef CONFIG_BOOTSTAGE
655 if (gd->flags & GD_FLG_SKIP_RELOC)
657 if (gd->new_bootstage) {
658 int size = bootstage_get_size();
660 debug("Copying bootstage from %p to %p, size %x\n",
661 gd->bootstage, gd->new_bootstage, size);
662 memcpy(gd->new_bootstage, gd->bootstage, size);
663 gd->bootstage = gd->new_bootstage;
664 bootstage_relocate();
671 static int reloc_bloblist(void)
673 #ifdef CONFIG_BLOBLIST
675 * Relocate only if we are supposed to send it
677 if ((gd->flags & GD_FLG_SKIP_RELOC) &&
678 CONFIG_BLOBLIST_SIZE == CONFIG_BLOBLIST_SIZE_RELOC) {
679 debug("Not relocating bloblist\n");
682 if (gd->new_bloblist) {
683 int size = CONFIG_BLOBLIST_SIZE;
685 debug("Copying bloblist from %p to %p, size %x\n",
686 gd->bloblist, gd->new_bloblist, size);
687 bloblist_reloc(gd->new_bloblist, CONFIG_BLOBLIST_SIZE_RELOC,
689 gd->bloblist = gd->new_bloblist;
696 static int setup_reloc(void)
698 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
699 #ifdef CONFIG_SYS_TEXT_BASE
701 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
702 #elif defined(CONFIG_MICROBLAZE)
703 gd->reloc_off = gd->relocaddr - (u32)_start;
704 #elif defined(CONFIG_M68K)
706 * On all ColdFire arch cpu, monitor code starts always
707 * just after the default vector table location, so at 0x400
709 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
710 #elif !defined(CONFIG_SANDBOX)
711 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
716 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
718 if (gd->flags & GD_FLG_SKIP_RELOC) {
719 debug("Skipping relocation due to flag\n");
721 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
722 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
723 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
730 #ifdef CONFIG_OF_BOARD_FIXUP
731 static int fix_fdt(void)
733 return board_fix_fdt((void *)gd->fdt_blob);
737 /* ARM calls relocate_code from its crt0.S */
738 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
739 !CONFIG_IS_ENABLED(X86_64)
741 static int jump_to_copy(void)
743 if (gd->flags & GD_FLG_SKIP_RELOC)
746 * x86 is special, but in a nice way. It uses a trampoline which
747 * enables the dcache if possible.
749 * For now, other archs use relocate_code(), which is implemented
750 * similarly for all archs. When we do generic relocation, hopefully
751 * we can make all archs enable the dcache prior to relocation.
753 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
755 * SDRAM and console are now initialised. The final stack can now
756 * be setup in SDRAM. Code execution will continue in Flash, but
757 * with the stack in SDRAM and Global Data in temporary memory
760 arch_setup_gd(gd->new_gd);
761 board_init_f_r_trampoline(gd->start_addr_sp);
763 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
770 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
771 static int initf_bootstage(void)
773 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
774 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
777 ret = bootstage_init(!from_spl);
781 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
782 CONFIG_BOOTSTAGE_STASH_SIZE);
784 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
785 if (ret && ret != -ENOENT) {
786 debug("Failed to unstash bootstage: err=%d\n", ret);
791 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
796 static int initf_dm(void)
798 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
801 bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f");
802 ret = dm_init_and_scan(true);
803 bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F);
807 if (IS_ENABLED(CONFIG_TIMER_EARLY)) {
808 ret = dm_timer_init();
817 /* Architecture-specific memory reservation */
818 __weak int reserve_arch(void)
823 __weak int checkcpu(void)
828 __weak int clear_bss(void)
833 static int misc_init_f(void)
835 return event_notify_null(EVT_MISC_INIT_F);
838 static const init_fnc_t init_sequence_f[] = {
840 #ifdef CONFIG_OF_CONTROL
843 #ifdef CONFIG_TRACE_EARLY
848 initf_bootstage, /* uses its own timer, so does not need DM */
851 #ifdef CONFIG_BLOBLIST
855 #if defined(CONFIG_CONSOLE_RECORD_INIT_F)
858 #if defined(CONFIG_HAVE_FSP)
861 arch_cpu_init, /* basic arch cpu dependent setup */
862 mach_cpu_init, /* SoC/machine dependent CPU setup */
864 #if defined(CONFIG_BOARD_EARLY_INIT_F)
867 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
868 /* get CPU and bus clocks according to the environment variable */
869 get_clocks, /* get CPU and bus clocks (etc.) */
871 #if !defined(CONFIG_M68K)
872 timer_init, /* initialize timer */
874 #if defined(CONFIG_BOARD_POSTCLK_INIT)
877 env_init, /* initialize environment */
878 init_baud_rate, /* initialze baudrate settings */
879 serial_init, /* serial communications setup */
880 console_init_f, /* stage 1 init of console */
881 display_options, /* say that we are here */
882 display_text_info, /* show debugging info if required */
884 #if defined(CONFIG_SYSRESET)
887 #if defined(CONFIG_DISPLAY_CPUINFO)
888 print_cpuinfo, /* display cpu info (and speed) */
890 #if defined(CONFIG_DTB_RESELECT)
893 #if defined(CONFIG_DISPLAY_BOARDINFO)
896 INIT_FUNC_WATCHDOG_INIT
898 INIT_FUNC_WATCHDOG_RESET
899 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
902 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
906 dram_init, /* configure available RAM banks */
910 INIT_FUNC_WATCHDOG_RESET
911 #if defined(CONFIG_SYS_DRAM_TEST)
913 #endif /* CONFIG_SYS_DRAM_TEST */
914 INIT_FUNC_WATCHDOG_RESET
919 INIT_FUNC_WATCHDOG_RESET
921 * Now that we have DRAM mapped and working, we can
922 * relocate the code and continue running from DRAM.
924 * Reserve memory at end of RAM for (top down in that order):
925 * - area that won't get touched by U-Boot and Linux (optional)
926 * - kernel log buffer
930 * - board info struct
933 #ifdef CONFIG_OF_BOARD_FIXUP
954 INIT_FUNC_WATCHDOG_RESET
957 INIT_FUNC_WATCHDOG_RESET
962 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
967 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
968 !CONFIG_IS_ENABLED(X86_64)
974 void board_init_f(ulong boot_flags)
976 gd->flags = boot_flags;
977 gd->have_console = 0;
979 if (initcall_run_list(init_sequence_f))
982 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
983 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
985 /* NOTREACHED - jump_to_copy() does not return */
990 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
992 * For now this code is only used on x86.
994 * init_sequence_f_r is the list of init functions which are run when
995 * U-Boot is executing from Flash with a semi-limited 'C' environment.
996 * The following limitations must be considered when implementing an
998 * - 'static' variables are read-only
999 * - Global Data (gd->xxx) is read/write
1001 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1002 * supported). It _should_, if possible, copy global data to RAM and
1003 * initialise the CPU caches (to speed up the relocation process)
1005 * NOTE: At present only x86 uses this route, but it is intended that
1006 * all archs will move to this when generic relocation is implemented.
1008 static const init_fnc_t init_sequence_f_r[] = {
1009 #if !CONFIG_IS_ENABLED(X86_64)
1016 void board_init_f_r(void)
1018 if (initcall_run_list(init_sequence_f_r))
1022 * The pre-relocation drivers may be using memory that has now gone
1023 * away. Mark serial as unavailable - this will fall back to the debug
1024 * UART if available.
1026 * Do the same with log drivers since the memory may not be available.
1028 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
1034 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1035 * Transfer execution from Flash to RAM by calculating the address
1036 * of the in-RAM copy of board_init_r() and calling it
1038 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
1040 /* NOTREACHED - board_init_r() does not return */
1043 #endif /* CONFIG_X86 */