1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
19 #include <env_internal.h>
34 #include <status_led.h>
40 #ifdef CONFIG_MACH_TYPE
41 #include <asm/mach-types.h>
43 #if defined(CONFIG_MP) && defined(CONFIG_PPC)
47 #include <asm/sections.h>
49 #include <linux/errno.h>
52 * Pointer to initial global data area
54 * Here we initialize it if needed.
56 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
57 #undef XTRN_DECLARE_GLOBAL_DATA_PTR
58 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
59 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
61 DECLARE_GLOBAL_DATA_PTR;
65 * TODO(sjg@chromium.org): IMO this code should be
66 * refactored to a single function, something like:
68 * void led_set_state(enum led_colour_t colour, int on);
70 /************************************************************************
71 * Coloured LED functionality
72 ************************************************************************
73 * May be supplied by boards if desired
75 __weak void coloured_LED_init(void) {}
76 __weak void red_led_on(void) {}
77 __weak void red_led_off(void) {}
78 __weak void green_led_on(void) {}
79 __weak void green_led_off(void) {}
80 __weak void yellow_led_on(void) {}
81 __weak void yellow_led_off(void) {}
82 __weak void blue_led_on(void) {}
83 __weak void blue_led_off(void) {}
86 * Why is gd allocated a register? Prior to reloc it might be better to
87 * just pass it around to each function in this file?
89 * After reloc one could argue that it is hardly used and doesn't need
90 * to be in a register. Or if it is it should perhaps hold pointers to all
91 * global data for all modules, so that post-reloc we can avoid the massive
92 * literal pool we get on ARM. Or perhaps just encourage each module to use
96 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
97 static int init_func_watchdog_init(void)
99 # if defined(CONFIG_HW_WATCHDOG) && \
100 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
101 defined(CONFIG_SH) || \
102 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
103 defined(CONFIG_IMX_WATCHDOG))
105 puts(" Watchdog enabled\n");
112 int init_func_watchdog_reset(void)
118 #endif /* CONFIG_WATCHDOG */
120 __weak void board_add_ram_info(int use_default)
122 /* please define platform specific board_add_ram_info() */
125 static int init_baud_rate(void)
127 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
131 static int display_text_info(void)
133 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
134 ulong bss_start, bss_end, text_base;
136 bss_start = (ulong)&__bss_start;
137 bss_end = (ulong)&__bss_end;
139 #ifdef CONFIG_SYS_TEXT_BASE
140 text_base = CONFIG_SYS_TEXT_BASE;
142 text_base = CONFIG_SYS_MONITOR_BASE;
145 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
146 text_base, bss_start, bss_end);
152 #ifdef CONFIG_SYSRESET
153 static int print_resetinfo(void)
159 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
161 debug("%s: No sysreset device found (error: %d)\n",
163 /* Not all boards have sysreset drivers available during early
164 * boot, so don't fail if one can't be found.
169 if (!sysreset_get_status(dev, status, sizeof(status)))
170 printf("%s", status);
176 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
177 static int print_cpuinfo(void)
183 ret = uclass_first_device_err(UCLASS_CPU, &dev);
185 debug("%s: Could not get CPU device (err = %d)\n",
190 ret = cpu_get_desc(dev, desc, sizeof(desc));
192 debug("%s: Could not get CPU description (err = %d)\n",
197 printf("CPU: %s\n", desc);
203 static int announce_dram_init(void)
209 static int show_dram_config(void)
211 unsigned long long size;
213 #ifdef CONFIG_NR_DRAM_BANKS
216 debug("\nRAM Configuration:\n");
217 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
218 size += gd->bd->bi_dram[i].size;
219 debug("Bank #%d: %llx ", i,
220 (unsigned long long)(gd->bd->bi_dram[i].start));
222 print_size(gd->bd->bi_dram[i].size, "\n");
230 print_size(size, "");
231 board_add_ram_info(0);
237 __weak int dram_init_banksize(void)
239 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
240 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
241 gd->bd->bi_dram[0].size = get_effective_memsize();
247 #if defined(CONFIG_SYS_I2C)
248 static int init_func_i2c(void)
251 #ifdef CONFIG_SYS_I2C
254 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
261 #if defined(CONFIG_VID)
262 __weak int init_func_vid(void)
268 static int setup_mon_len(void)
270 #if defined(__ARM__) || defined(__MICROBLAZE__)
271 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
272 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
273 gd->mon_len = (ulong)&_end - (ulong)_init;
274 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
275 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
276 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
277 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
278 #elif defined(CONFIG_SYS_MONITOR_BASE)
279 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
280 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
285 static int setup_spl_handoff(void)
287 #if CONFIG_IS_ENABLED(HANDOFF)
288 gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
289 sizeof(struct spl_handoff));
290 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
296 __weak int arch_cpu_init(void)
301 __weak int mach_cpu_init(void)
306 /* Get the top of usable RAM */
307 __weak ulong board_get_usable_ram_top(ulong total_size)
309 #ifdef CONFIG_SYS_SDRAM_BASE
311 * Detect whether we have so much RAM that it goes past the end of our
312 * 32-bit address space. If so, clip the usable RAM so it doesn't.
314 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
316 * Will wrap back to top of 32-bit space when reservations
324 static int setup_dest_addr(void)
326 debug("Monitor len: %08lX\n", gd->mon_len);
328 * Ram is setup, size stored in gd !!
330 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
331 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
333 * Subtract specified amount of memory to hide so that it won't
334 * get "touched" at all by U-Boot. By fixing up gd->ram_size
335 * the Linux kernel should now get passed the now "corrected"
336 * memory size and won't touch it either. This should work
337 * for arch/ppc and arch/powerpc. Only Linux board ports in
338 * arch/powerpc with bootwrapper support, that recalculate the
339 * memory size from the SDRAM controller setup will have to
342 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
344 #ifdef CONFIG_SYS_SDRAM_BASE
345 gd->ram_base = CONFIG_SYS_SDRAM_BASE;
347 gd->ram_top = gd->ram_base + get_effective_memsize();
348 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
349 gd->relocaddr = gd->ram_top;
350 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
351 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
353 * We need to make sure the location we intend to put secondary core
354 * boot code is reserved and not used by any part of u-boot
356 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
357 gd->relocaddr = determine_mp_bootpg(NULL);
358 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
365 /* reserve protected RAM */
366 static int reserve_pram(void)
370 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
371 gd->relocaddr -= (reg << 10); /* size is in kB */
372 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
376 #endif /* CONFIG_PRAM */
378 /* Round memory pointer down to next 4 kB limit */
379 static int reserve_round_4k(void)
381 gd->relocaddr &= ~(4096 - 1);
386 __weak int reserve_mmu(void)
388 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
389 /* reserve TLB table */
390 gd->arch.tlb_size = PGTABLE_SIZE;
391 gd->relocaddr -= gd->arch.tlb_size;
393 /* round down to next 64 kB limit */
394 gd->relocaddr &= ~(0x10000 - 1);
396 gd->arch.tlb_addr = gd->relocaddr;
397 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
398 gd->arch.tlb_addr + gd->arch.tlb_size);
400 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
402 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
403 * with location within secure ram.
405 gd->arch.tlb_allocated = gd->arch.tlb_addr;
413 static int reserve_video(void)
415 #ifdef CONFIG_DM_VIDEO
419 addr = gd->relocaddr;
420 ret = video_reserve(&addr);
423 gd->relocaddr = addr;
424 #elif defined(CONFIG_LCD)
425 # ifdef CONFIG_FB_ADDR
426 gd->fb_base = CONFIG_FB_ADDR;
428 /* reserve memory for LCD display (always full pages) */
429 gd->relocaddr = lcd_setmem(gd->relocaddr);
430 gd->fb_base = gd->relocaddr;
431 # endif /* CONFIG_FB_ADDR */
437 static int reserve_trace(void)
440 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
441 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
442 debug("Reserving %luk for trace data at: %08lx\n",
443 (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
449 static int reserve_uboot(void)
451 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
453 * reserve memory for U-Boot code, data & bss
454 * round down to next 4 kB limit
456 gd->relocaddr -= gd->mon_len;
457 gd->relocaddr &= ~(4096 - 1);
458 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
459 /* round down to next 64 kB limit so that IVPR stays aligned */
460 gd->relocaddr &= ~(65536 - 1);
463 debug("Reserving %ldk for U-Boot at: %08lx\n",
464 gd->mon_len >> 10, gd->relocaddr);
467 gd->start_addr_sp = gd->relocaddr;
472 #ifdef CONFIG_SYS_NONCACHED_MEMORY
473 static int reserve_noncached(void)
476 * The value of gd->start_addr_sp must match the value of malloc_start
477 * calculated in boatrd_f.c:initr_malloc(), which is passed to
478 * board_r.c:mem_malloc_init() and then used by
479 * cache.c:noncached_init()
481 * These calculations must match the code in cache.c:noncached_init()
483 gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
485 gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
487 debug("Reserving %dM for noncached_alloc() at: %08lx\n",
488 CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
494 /* reserve memory for malloc() area */
495 static int reserve_malloc(void)
497 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
498 debug("Reserving %dk for malloc() at: %08lx\n",
499 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
500 #ifdef CONFIG_SYS_NONCACHED_MEMORY
507 /* (permanently) allocate a Board Info struct */
508 static int reserve_board(void)
511 gd->start_addr_sp -= sizeof(bd_t);
512 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
513 memset(gd->bd, '\0', sizeof(bd_t));
514 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
515 sizeof(bd_t), gd->start_addr_sp);
520 static int setup_machine(void)
522 #ifdef CONFIG_MACH_TYPE
523 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
528 static int reserve_global_data(void)
530 gd->start_addr_sp -= sizeof(gd_t);
531 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
532 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
533 sizeof(gd_t), gd->start_addr_sp);
537 static int reserve_fdt(void)
539 #ifndef CONFIG_OF_EMBED
541 * If the device tree is sitting immediately above our image then we
542 * must relocate it. If it is embedded in the data section, then it
543 * will be relocated with other data.
546 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
548 gd->start_addr_sp -= gd->fdt_size;
549 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
550 debug("Reserving %lu Bytes for FDT at: %08lx\n",
551 gd->fdt_size, gd->start_addr_sp);
558 static int reserve_bootstage(void)
560 #ifdef CONFIG_BOOTSTAGE
561 int size = bootstage_get_size();
563 gd->start_addr_sp -= size;
564 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
565 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
572 __weak int arch_reserve_stacks(void)
577 static int reserve_stacks(void)
579 /* make stack pointer 16-byte aligned */
580 gd->start_addr_sp -= 16;
581 gd->start_addr_sp &= ~0xf;
584 * let the architecture-specific code tailor gd->start_addr_sp and
587 return arch_reserve_stacks();
590 static int reserve_bloblist(void)
592 #ifdef CONFIG_BLOBLIST
593 gd->start_addr_sp &= ~0xf;
594 gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE;
595 gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
601 static int display_new_sp(void)
603 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
608 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
610 static int setup_board_part1(void)
615 * Save local variables to board info struct
617 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
618 bd->bi_memsize = gd->ram_size; /* size in bytes */
620 #ifdef CONFIG_SYS_SRAM_BASE
621 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
622 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
625 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
626 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
628 #if defined(CONFIG_M68K)
629 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
631 #if defined(CONFIG_MPC83xx)
632 bd->bi_immrbar = CONFIG_SYS_IMMR;
639 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
640 static int setup_board_part2(void)
644 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
645 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
646 #if defined(CONFIG_CPM2)
647 bd->bi_cpmfreq = gd->arch.cpm_clk;
648 bd->bi_brgfreq = gd->arch.brg_clk;
649 bd->bi_sccfreq = gd->arch.scc_clk;
650 bd->bi_vco = gd->arch.vco_out;
651 #endif /* CONFIG_CPM2 */
652 #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
653 bd->bi_pcifreq = gd->pci_clk;
655 #if defined(CONFIG_EXTRA_CLOCK)
656 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
657 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
658 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
666 static int init_post(void)
668 post_bootmode_init();
669 post_run(NULL, POST_ROM | post_bootmode_get(0));
675 static int reloc_fdt(void)
677 #ifndef CONFIG_OF_EMBED
678 if (gd->flags & GD_FLG_SKIP_RELOC)
681 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
682 gd->fdt_blob = gd->new_fdt;
689 static int reloc_bootstage(void)
691 #ifdef CONFIG_BOOTSTAGE
692 if (gd->flags & GD_FLG_SKIP_RELOC)
694 if (gd->new_bootstage) {
695 int size = bootstage_get_size();
697 debug("Copying bootstage from %p to %p, size %x\n",
698 gd->bootstage, gd->new_bootstage, size);
699 memcpy(gd->new_bootstage, gd->bootstage, size);
700 gd->bootstage = gd->new_bootstage;
701 bootstage_relocate();
708 static int reloc_bloblist(void)
710 #ifdef CONFIG_BLOBLIST
711 if (gd->flags & GD_FLG_SKIP_RELOC)
713 if (gd->new_bloblist) {
714 int size = CONFIG_BLOBLIST_SIZE;
716 debug("Copying bloblist from %p to %p, size %x\n",
717 gd->bloblist, gd->new_bloblist, size);
718 memcpy(gd->new_bloblist, gd->bloblist, size);
719 gd->bloblist = gd->new_bloblist;
726 static int setup_reloc(void)
728 if (gd->flags & GD_FLG_SKIP_RELOC) {
729 debug("Skipping relocation due to flag\n");
733 #ifdef CONFIG_SYS_TEXT_BASE
735 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
736 #elif defined(CONFIG_M68K)
738 * On all ColdFire arch cpu, monitor code starts always
739 * just after the default vector table location, so at 0x400
741 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
742 #elif !defined(CONFIG_SANDBOX)
743 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
746 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
748 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
749 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
750 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
756 #ifdef CONFIG_OF_BOARD_FIXUP
757 static int fix_fdt(void)
759 return board_fix_fdt((void *)gd->fdt_blob);
763 /* ARM calls relocate_code from its crt0.S */
764 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
765 !CONFIG_IS_ENABLED(X86_64)
767 static int jump_to_copy(void)
769 if (gd->flags & GD_FLG_SKIP_RELOC)
772 * x86 is special, but in a nice way. It uses a trampoline which
773 * enables the dcache if possible.
775 * For now, other archs use relocate_code(), which is implemented
776 * similarly for all archs. When we do generic relocation, hopefully
777 * we can make all archs enable the dcache prior to relocation.
779 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
781 * SDRAM and console are now initialised. The final stack can now
782 * be setup in SDRAM. Code execution will continue in Flash, but
783 * with the stack in SDRAM and Global Data in temporary memory
786 arch_setup_gd(gd->new_gd);
787 board_init_f_r_trampoline(gd->start_addr_sp);
789 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
796 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
797 static int initf_bootstage(void)
799 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
800 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
803 ret = bootstage_init(!from_spl);
807 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
808 CONFIG_BOOTSTAGE_STASH_SIZE);
810 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
811 if (ret && ret != -ENOENT) {
812 debug("Failed to unstash bootstage: err=%d\n", ret);
817 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
822 static int initf_console_record(void)
824 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
825 return console_record_init();
831 static int initf_dm(void)
833 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
836 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
837 ret = dm_init_and_scan(true);
838 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
842 #ifdef CONFIG_TIMER_EARLY
843 ret = dm_timer_init();
851 /* Architecture-specific memory reservation */
852 __weak int reserve_arch(void)
857 __weak int arch_cpu_init_dm(void)
862 static const init_fnc_t init_sequence_f[] = {
864 #ifdef CONFIG_OF_CONTROL
867 #ifdef CONFIG_TRACE_EARLY
872 initf_bootstage, /* uses its own timer, so does not need DM */
873 #ifdef CONFIG_BLOBLIST
877 initf_console_record,
878 #if defined(CONFIG_HAVE_FSP)
881 arch_cpu_init, /* basic arch cpu dependent setup */
882 mach_cpu_init, /* SoC/machine dependent CPU setup */
885 #if defined(CONFIG_BOARD_EARLY_INIT_F)
888 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
889 /* get CPU and bus clocks according to the environment variable */
890 get_clocks, /* get CPU and bus clocks (etc.) */
892 #if !defined(CONFIG_M68K)
893 timer_init, /* initialize timer */
895 #if defined(CONFIG_BOARD_POSTCLK_INIT)
898 env_init, /* initialize environment */
899 init_baud_rate, /* initialze baudrate settings */
900 serial_init, /* serial communications setup */
901 console_init_f, /* stage 1 init of console */
902 display_options, /* say that we are here */
903 display_text_info, /* show debugging info if required */
904 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
907 #if defined(CONFIG_SYSRESET)
910 #if defined(CONFIG_DISPLAY_CPUINFO)
911 print_cpuinfo, /* display cpu info (and speed) */
913 #if defined(CONFIG_DTB_RESELECT)
916 #if defined(CONFIG_DISPLAY_BOARDINFO)
919 INIT_FUNC_WATCHDOG_INIT
920 #if defined(CONFIG_MISC_INIT_F)
923 INIT_FUNC_WATCHDOG_RESET
924 #if defined(CONFIG_SYS_I2C)
927 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
931 dram_init, /* configure available RAM banks */
935 INIT_FUNC_WATCHDOG_RESET
936 #if defined(CONFIG_SYS_DRAM_TEST)
938 #endif /* CONFIG_SYS_DRAM_TEST */
939 INIT_FUNC_WATCHDOG_RESET
944 INIT_FUNC_WATCHDOG_RESET
946 * Now that we have DRAM mapped and working, we can
947 * relocate the code and continue running from DRAM.
949 * Reserve memory at end of RAM for (top down in that order):
950 * - area that won't get touched by U-Boot and Linux (optional)
951 * - kernel log buffer
955 * - board info struct
979 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
983 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
984 INIT_FUNC_WATCHDOG_RESET
988 #ifdef CONFIG_OF_BOARD_FIXUP
991 INIT_FUNC_WATCHDOG_RESET
996 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
1001 #if defined(CONFIG_XTENSA)
1004 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
1005 !CONFIG_IS_ENABLED(X86_64)
1011 void board_init_f(ulong boot_flags)
1013 gd->flags = boot_flags;
1014 gd->have_console = 0;
1016 if (initcall_run_list(init_sequence_f))
1019 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
1020 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
1021 !defined(CONFIG_ARC)
1022 /* NOTREACHED - jump_to_copy() does not return */
1027 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
1029 * For now this code is only used on x86.
1031 * init_sequence_f_r is the list of init functions which are run when
1032 * U-Boot is executing from Flash with a semi-limited 'C' environment.
1033 * The following limitations must be considered when implementing an
1035 * - 'static' variables are read-only
1036 * - Global Data (gd->xxx) is read/write
1038 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1039 * supported). It _should_, if possible, copy global data to RAM and
1040 * initialise the CPU caches (to speed up the relocation process)
1042 * NOTE: At present only x86 uses this route, but it is intended that
1043 * all archs will move to this when generic relocation is implemented.
1045 static const init_fnc_t init_sequence_f_r[] = {
1046 #if !CONFIG_IS_ENABLED(X86_64)
1053 void board_init_f_r(void)
1055 if (initcall_run_list(init_sequence_f_r))
1059 * The pre-relocation drivers may be using memory that has now gone
1060 * away. Mark serial as unavailable - this will fall back to the debug
1061 * UART if available.
1063 * Do the same with log drivers since the memory may not be available.
1065 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
1071 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1072 * Transfer execution from Flash to RAM by calculating the address
1073 * of the in-RAM copy of board_init_r() and calling it
1075 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
1077 /* NOTREACHED - board_init_r() does not return */
1080 #endif /* CONFIG_X86 */