2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3 ; Copyright (c) 2012, Intel Corporation
7 ; Redistribution and use in source and binary forms, with or without
8 ; modification, are permitted provided that the following conditions are
11 ; * Redistributions of source code must retain the above copyright
12 ; notice, this list of conditions and the following disclaimer.
14 ; * Redistributions in binary form must reproduce the above copyright
15 ; notice, this list of conditions and the following disclaimer in the
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19 ; * Neither the name of the Intel Corporation nor the names of its
20 ; contributors may be used to endorse or promote products derived from
21 ; this software without specific prior written permission.
24 ; THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION "AS IS" AND ANY
25 ; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR
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31 ; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 ; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 ; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 ; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
38 * Conversion to GAS assembly and integration to libgcrypt
39 * by Jussi Kivilinna <jussi.kivilinna@iki.fi>
44 #if defined(HAVE_COMPATIBLE_GCC_AMD64_PLATFORM_AS) && \
45 defined(HAVE_INTEL_SYNTAX_PLATFORM_AS) && \
46 defined(HAVE_GCC_INLINE_ASM_AVX) && defined(USE_SHA512)
54 .intel_syntax noprefix
58 /* Virtual Registers */
60 digest = rsi /* ARG2 */
61 msglen = rdx /* ARG3 */
75 ; Local variables (stack frame)
76 ; Note: frame_size must be an odd multiple of 8 bytes to XMM align RSP
78 frame_W = 0 /* Message Schedule */
79 frame_W_size = (80 * 8)
80 frame_WK = ((frame_W) + (frame_W_size)) /* W[t] + K[t] | W[t+1] + K[t+1] */
81 frame_WK_size = (2 * 8)
82 frame_GPRSAVE = ((frame_WK) + (frame_WK_size))
83 frame_GPRSAVE_size = (5 * 8)
84 frame_size = ((frame_GPRSAVE) + (frame_GPRSAVE_size))
87 /* Useful QWORD "arrays" for simpler memory references */
88 #define MSG(i) msg + 8*(i) /* Input message (arg1) */
89 #define DIGEST(i) digest + 8*(i) /* Output Digest (arg2) */
90 #define K_t(i) .LK512 + 8*(i) ADD_RIP /* SHA Constants (static mem) */
91 #define W_t(i) rsp + frame_W + 8*(i) /* Message Schedule (stack frame) */
92 #define WK_2(i) rsp + frame_WK + 8*((i) % 2) /* W[t]+K[t] (stack frame) */
93 /* MSG, DIGEST, K_t, W_t are arrays */
94 /* WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even */
97 /* Rotate symbles a..h right */
110 /* shld is faster than ror on Intel Sandybridge */
111 shld \p1, \p1, (64 - \p2)
114 .macro SHA512_Round t
115 /* Compute Round %%t */
116 mov T1, f_64 /* T1 = f */
117 mov tmp0, e_64 /* tmp = e */
118 xor T1, g_64 /* T1 = f ^ g */
119 RORQ tmp0, 23 /* 41 ; tmp = e ror 23 */
120 and T1, e_64 /* T1 = (f ^ g) & e */
121 xor tmp0, e_64 /* tmp = (e ror 23) ^ e */
122 xor T1, g_64 /* T1 = ((f ^ g) & e) ^ g = CH(e,f,g) */
123 add T1, [WK_2(\t)] /* W[t] + K[t] from message scheduler */
124 RORQ tmp0, 4 /* 18 ; tmp = ((e ror 23) ^ e) ror 4 */
125 xor tmp0, e_64 /* tmp = (((e ror 23) ^ e) ror 4) ^ e */
126 mov T2, a_64 /* T2 = a */
127 add T1, h_64 /* T1 = CH(e,f,g) + W[t] + K[t] + h */
128 RORQ tmp0, 14 /* 14 ; tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e) */
129 add T1, tmp0 /* T1 = CH(e,f,g) + W[t] + K[t] + S1(e) */
130 mov tmp0, a_64 /* tmp = a */
131 xor T2, c_64 /* T2 = a ^ c */
132 and tmp0, c_64 /* tmp = a & c */
133 and T2, b_64 /* T2 = (a ^ c) & b */
134 xor T2, tmp0 /* T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c) */
135 mov tmp0, a_64 /* tmp = a */
136 RORQ tmp0, 5 /* 39 ; tmp = a ror 5 */
137 xor tmp0, a_64 /* tmp = (a ror 5) ^ a */
138 add d_64, T1 /* e(next_state) = d + T1 */
139 RORQ tmp0, 6 /* 34 ; tmp = ((a ror 5) ^ a) ror 6 */
140 xor tmp0, a_64 /* tmp = (((a ror 5) ^ a) ror 6) ^ a */
141 lea h_64, [T1 + T2] /* a(next_state) = T1 + Maj(a,b,c) */
142 RORQ tmp0, 28 /* 28 ; tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a) */
143 add h_64, tmp0 /* a(next_state) = T1 + Maj(a,b,c) S0(a) */
147 .macro SHA512_2Sched_2Round_avx t
148 /* ; Compute rounds %%t-2 and %%t-1
149 ; Compute message schedule QWORDS %%t and %%t+1
151 ; Two rounds are computed based on the values for K[t-2]+W[t-2] and
152 ; K[t-1]+W[t-1] which were previously stored at WK_2 by the message
154 ; The two new schedule QWORDS are stored at [W_t(%%t)] and [W_t(%%t+1)].
155 ; They are then added to their respective SHA512 constants at
156 ; [K_t(%%t)] and [K_t(%%t+1)] and stored at dqword [WK_2(%%t)]
157 ; For brievity, the comments following vectored instructions only refer to
158 ; the first of a pair of QWORDS.
159 ; Eg. XMM4=W[t-2] really means XMM4={W[t-2]|W[t-1]}
160 ; The computation of the message schedule and the rounds are tightly
161 ; stitched to take advantage of instruction-level parallelism.
162 ; For clarity, integer instructions (for the rounds calculation) are indented
163 ; by one tab. Vectored instructions (for the message scheduler) are indented
166 vmovdqa xmm4, [W_t(\t-2)] /* XMM4 = W[t-2] */
167 vmovdqu xmm5, [W_t(\t-15)] /* XMM5 = W[t-15] */
169 vpsrlq xmm0, xmm4, 61 /* XMM0 = W[t-2]>>61 */
171 vpsrlq xmm6, xmm5, 1 /* XMM6 = W[t-15]>>1 */
173 RORQ tmp0, 23 /* 41 */
174 vpsrlq xmm1, xmm4, 19 /* XMM1 = W[t-2]>>19 */
177 vpxor xmm0, xmm0, xmm1 /* XMM0 = W[t-2]>>61 ^ W[t-2]>>19 */
180 vpsrlq xmm7, xmm5, 8 /* XMM7 = W[t-15]>>8 */
181 RORQ tmp0, 4 /* 18 */
182 vpsrlq xmm2, xmm4, 6 /* XMM2 = W[t-2]>>6 */
186 vpxor xmm6, xmm6, xmm7 /* XMM6 = W[t-15]>>1 ^ W[t-15]>>8 */
187 RORQ tmp0, 14 /* 14 */
189 vpsrlq xmm8, xmm5, 7 /* XMM8 = W[t-15]>>7 */
192 vpsllq xmm3, xmm4, (64-61) /* XMM3 = W[t-2]<<3 */
195 vpxor xmm2, xmm2, xmm3 /* XMM2 = W[t-2]>>6 ^ W[t-2]<<3 */
198 vpsllq xmm9, xmm5, (64-1) /* XMM9 = W[t-15]<<63 */
199 RORQ tmp0, 5 /* 39 */
200 vpxor xmm8, xmm8, xmm9 /* XMM8 = W[t-15]>>7 ^ W[t-15]<<63 */
203 RORQ tmp0, 6 /* 34 */
205 vpxor xmm6, xmm6, xmm8 /* XMM6 = W[t-15]>>1 ^ W[t-15]>>8 ^ W[t-15]>>7 ^ W[t-15]<<63 */
207 RORQ tmp0, 28 /* 28 */
208 vpsllq xmm4, xmm4, (64-19) /* XMM4 = W[t-2]<<25 */
211 vpxor xmm0, xmm0, xmm4 /* XMM0 = W[t-2]>>61 ^ W[t-2]>>19 ^ W[t-2]<<25 */
213 vpxor xmm0, xmm0, xmm2 /* XMM0 = s1(W[t-2]) */
216 vpaddq xmm0, xmm0, [W_t(\t-16)] /* XMM0 = s1(W[t-2]) + W[t-16] */
217 vmovdqu xmm1, [W_t(\t- 7)] /* XMM1 = W[t-7] */
218 RORQ tmp0, 23 /* 41 */
222 vpsllq xmm5, xmm5, (64-8) /* XMM5 = W[t-15]<<56 */
224 vpxor xmm6, xmm6, xmm5 /* XMM6 = s0(W[t-15]) */
225 RORQ tmp0, 4 /* 18 */
226 vpaddq xmm0, xmm0, xmm6 /* XMM0 = s1(W[t-2]) + W[t-16] + s0(W[t-15]) */
228 vpaddq xmm0, xmm0, xmm1 /* XMM0 = W[t] = s1(W[t-2]) + W[t-7] + s0(W[t-15]) + W[t-16] */
231 RORQ tmp0, 14 /* 14 */
233 vmovdqa [W_t(\t)], xmm0 /* Store W[t] */
234 vpaddq xmm0, xmm0, [K_t(t)] /* Compute W[t]+K[t] */
235 vmovdqa [WK_2(t)], xmm0 /* Store W[t]+K[t] for next rounds */
242 RORQ tmp0, 5 /* 39 */
245 RORQ tmp0, 6 /* 34 */
248 RORQ tmp0, 28 /* 28 */
254 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
255 ; void sha512_avx(const void* M, void* D, uint64_t L);
256 ; Purpose: Updates the SHA512 digest stored at D with the message stored in M.
257 ; The size of the message pointed to by M must be an integer multiple of SHA512
259 ; L is the message length in SHA512 blocks
261 .globl _gcry_sha512_transform_amd64_avx
262 .type _gcry_sha512_transform_amd64_avx,@function;
264 _gcry_sha512_transform_amd64_avx:
272 /* Allocate Stack Space */
276 mov [rsp + frame_GPRSAVE + 8 * 0], rbx
277 mov [rsp + frame_GPRSAVE + 8 * 1], r12
278 mov [rsp + frame_GPRSAVE + 8 * 2], r13
279 mov [rsp + frame_GPRSAVE + 8 * 3], r14
280 mov [rsp + frame_GPRSAVE + 8 * 4], r15
284 /* Load state variables */
285 mov a_64, [DIGEST(0)]
286 mov b_64, [DIGEST(1)]
287 mov c_64, [DIGEST(2)]
288 mov d_64, [DIGEST(3)]
289 mov e_64, [DIGEST(4)]
290 mov f_64, [DIGEST(5)]
291 mov g_64, [DIGEST(6)]
292 mov h_64, [DIGEST(7)]
296 /* (80 rounds) / (2 rounds/iteration) + (1 iteration) */
297 /* +1 iteration because the scheduler leads hashing by 1 iteration */
300 vmovdqa xmm1, [.LXMM_QWORD_BSWAP ADD_RIP]
301 vmovdqu xmm0, [MSG(t)]
302 vpshufb xmm0, xmm0, xmm1 /* BSWAP */
303 vmovdqa [W_t(t)], xmm0 /* Store Scheduled Pair */
304 vpaddq xmm0, xmm0, [K_t(t)] /* Compute W[t]+K[t] */
305 vmovdqa [WK_2(t)], xmm0 /* Store into WK for rounds */
307 /* BSWAP 2 QWORDS, Compute 2 Rounds */
308 vmovdqu xmm0, [MSG(t)]
309 vpshufb xmm0, xmm0, xmm1 /* BSWAP */
310 SHA512_Round (t - 2) /* Round t-2 */
311 vmovdqa [W_t(t)], xmm0 /* Store Scheduled Pair */
312 vpaddq xmm0, xmm0, [K_t(t)] /* Compute W[t]+K[t] */
313 SHA512_Round (t - 1) /* Round t-1 */
314 vmovdqa [WK_2(t)], xmm0 /* W[t]+K[t] into WK */
316 /* Schedule 2 QWORDS; Compute 2 Rounds */
317 SHA512_2Sched_2Round_avx t
319 /* Compute 2 Rounds */
327 add [DIGEST(0)], a_64
328 add [DIGEST(1)], b_64
329 add [DIGEST(2)], c_64
330 add [DIGEST(3)], d_64
331 add [DIGEST(4)], e_64
332 add [DIGEST(5)], f_64
333 add [DIGEST(6)], g_64
334 add [DIGEST(7)], h_64
336 /* Advance to next message block */
342 mov rbx, [rsp + frame_GPRSAVE + 8 * 0]
343 mov r12, [rsp + frame_GPRSAVE + 8 * 1]
344 mov r13, [rsp + frame_GPRSAVE + 8 * 2]
345 mov r14, [rsp + frame_GPRSAVE + 8 * 3]
346 mov r15, [rsp + frame_GPRSAVE + 8 * 4]
348 /* Restore Stack Pointer */
353 /* Return stack burn depth */
360 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
368 /* Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb. */
370 .octa 0x08090a0b0c0d0e0f0001020304050607
372 /* K[t] used in SHA512 hashing */
374 .quad 0x428a2f98d728ae22,0x7137449123ef65cd
375 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
376 .quad 0x3956c25bf348b538,0x59f111f1b605d019
377 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
378 .quad 0xd807aa98a3030242,0x12835b0145706fbe
379 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
380 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
381 .quad 0x9bdc06a725c71235,0xc19bf174cf692694
382 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
383 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
384 .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
385 .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
386 .quad 0x983e5152ee66dfab,0xa831c66d2db43210
387 .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
388 .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
389 .quad 0x06ca6351e003826f,0x142929670a0e6e70
390 .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
391 .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
392 .quad 0x650a73548baf63de,0x766a0abb3c77b2a8
393 .quad 0x81c2c92e47edaee6,0x92722c851482353b
394 .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
395 .quad 0xc24b8b70d0f89791,0xc76c51a30654be30
396 .quad 0xd192e819d6ef5218,0xd69906245565a910
397 .quad 0xf40e35855771202a,0x106aa07032bbd1b8
398 .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
399 .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
400 .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
401 .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
402 .quad 0x748f82ee5defb2fc,0x78a5636f43172f60
403 .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
404 .quad 0x90befffa23631e28,0xa4506cebde82bde9
405 .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
406 .quad 0xca273eceea26619c,0xd186b8c721c0c207
407 .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
408 .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
409 .quad 0x113f9804bef90dae,0x1b710b35131c471b
410 .quad 0x28db77f523047d84,0x32caab7b40c72493
411 .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
412 .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
413 .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817