2 * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
25 #include <spd_sdram.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 int board_early_init_f(void)
35 /* TBS: Setup the GPIO access for the user LEDs */
36 mfsdr(sdr_pfc0, sdrreg);
37 mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
38 out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
44 /* Setup the external bus controller/chip selects */
45 mtebc(pb0ap, 0x04055200); /* 16MB Strata FLASH */
46 mtebc(pb0cr, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */
47 mtebc(pb1ap, 0x04055200); /* 512KB Socketed AMD FLASH */
48 mtebc(pb1cr, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */
49 mtebc(pb6ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
50 mtebc(pb6cr, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */
51 mtebc(pb7ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
52 mtebc(pb7cr, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */
55 * Setup the interrupt controller polarities, triggers, etc.
57 * Because of the interrupt handling rework to handle 440GX interrupts
58 * with the common code, we needed to change names of the UIC registers.
59 * Here the new relationship:
61 * U-Boot name 440GX name
62 * -----------------------
68 mtdcr(uic1sr, 0xffffffff); /* clear all */
69 mtdcr(uic1er, 0x00000000); /* disable all */
70 mtdcr(uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
71 mtdcr(uic1pr, 0xfffffe00); /* per ref-board manual */
72 mtdcr(uic1tr, 0x01c00000); /* per ref-board manual */
73 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
74 mtdcr(uic1sr, 0xffffffff); /* clear all */
76 mtdcr(uic2sr, 0xffffffff); /* clear all */
77 mtdcr(uic2er, 0x00000000); /* disable all */
78 mtdcr(uic2cr, 0x00000000); /* all non-critical */
79 mtdcr(uic2pr, 0xffffc0ff); /* per ref-board manual */
80 mtdcr(uic2tr, 0x00ff8000); /* per ref-board manual */
81 mtdcr(uic2vr, 0x00000001); /* int31 highest, base=0x000 */
82 mtdcr(uic2sr, 0xffffffff); /* clear all */
84 mtdcr(uic3sr, 0xffffffff); /* clear all */
85 mtdcr(uic3er, 0x00000000); /* disable all */
86 mtdcr(uic3cr, 0x00000000); /* all non-critical */
87 mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
88 mtdcr(uic3tr, 0x00ff8c0f); /* per ref-board manual */
89 mtdcr(uic3vr, 0x00000001); /* int31 highest, base=0x000 */
90 mtdcr(uic3sr, 0xffffffff); /* clear all */
92 mtdcr(uic0sr, 0xfc000000); /* clear all */
93 mtdcr(uic0er, 0x00000000); /* disable all */
94 mtdcr(uic0cr, 0x00000000); /* all non-critical */
95 mtdcr(uic0pr, 0xfc000000); /* */
96 mtdcr(uic0tr, 0x00000000); /* */
97 mtdcr(uic0vr, 0x00000001); /* */
106 printf("Board: XES XPedite1000 440GX\n");
111 phys_size_t initdram(int board_type)
117 * This routine is called just prior to registering the hose and gives
118 * the board the opportunity to check things. Returning a value of zero
119 * indicates that things are bad & PCI initialization should be aborted.
121 * Different boards may wish to customize the pci controller structure
122 * (add regions, override default access routines, etc) or perform
123 * certain pre-initialization actions.
126 #if defined(CONFIG_PCI)
127 int pci_pre_init(struct pci_controller * hose)
131 /* See if we're supposed to setup the pci */
132 mfsdr(sdr_sdstp1, strap);
133 if ((strap & 0x00010000) == 0)
136 #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
137 /* Setup System Device Register PCIX0_XCR */
138 mfsdr(sdr_xcr, strap);
140 mtsdr(sdr_xcr, strap);
145 #endif /* defined(CONFIG_PCI) */
147 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
149 * The bootstrap configuration provides default settings for the pci
150 * inbound map (PIM). But the bootstrap config choices are limited and
151 * may not be sufficient for a given board.
153 void pci_target_init(struct pci_controller * hose)
155 /* Disable everything */
156 out32r(PCIX0_PIM0SA, 0);
157 out32r(PCIX0_PIM1SA, 0);
158 out32r(PCIX0_PIM2SA, 0);
159 out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
162 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
163 * options to not support sizes such as 128/256 MB.
165 out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
166 out32r(PCIX0_PIM0LAH, 0);
167 out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
169 out32r(PCIX0_BAR0, 0);
171 /* Program the board's subsystem id/vendor id */
172 out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
173 out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
175 out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
177 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
179 #if defined(CONFIG_PCI)
181 * This routine is called to determine if a pci scan should be
182 * performed. With various hardware environments (especially cPCI and
183 * PPMC) it's insufficient to depend on the state of the arbiter enable
184 * bit in the strap register, or generic host/adapter assumptions.
186 * Rather than hard-code a bad assumption in the general 440 code, the
187 * 440 pci code requires the board to decide at runtime.
189 * Return 0 for adapter mode, non-zero for host (monarch) mode.
191 int is_pci_host(struct pci_controller *hose)
193 return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
195 #endif /* defined(CONFIG_PCI) */
199 * Returns 1 if keys pressed to start the power-on long-running tests
200 * Called from board_init_f().
202 int post_hotkeys_pressed(void)
207 void post_word_store(ulong a)
209 volatile ulong *save_addr =
210 (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
215 ulong post_word_load(void)
217 volatile ulong *save_addr =
218 (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);