2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
18 #include <dwc3-uboot.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
26 !defined(CONFIG_SPL_BUILD)
27 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
33 } zynqmp_devices[] = {
116 { /* For testing purpose only */
160 int chip_id(unsigned char id)
165 if (current_el() != 3) {
166 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
175 * regs[0][31:0] = status of the operation
176 * regs[0][63:32] = CSU.IDCODE register
177 * regs[1][31:0] = CSU.version register
178 * regs[1][63:32] = CSU.IDCODE2 register
182 regs.regs[0] = upper_32_bits(regs.regs[0]);
183 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
184 ZYNQMP_CSU_IDCODE_SVD_MASK;
185 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
189 regs.regs[1] = lower_32_bits(regs.regs[1]);
190 regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
194 regs.regs[1] = lower_32_bits(regs.regs[1]);
195 regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
199 printf("%s, Invalid Req:0x%x\n", __func__, id);
204 val = readl(ZYNQMP_CSU_IDCODE_ADDR);
205 val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
206 ZYNQMP_CSU_IDCODE_SVD_MASK;
207 val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
210 val = readl(ZYNQMP_CSU_VER_ADDR);
211 val &= ZYNQMP_CSU_SILICON_VER_MASK;
214 printf("%s, Invalid Req:0x%x\n", __func__, id);
221 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
222 !defined(CONFIG_SPL_BUILD)
223 static char *zynqmp_get_silicon_idcode_name(void)
227 id = chip_id(IDCODE);
228 ver = chip_id(IDCODE2);
230 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
231 if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
232 return zynqmp_devices[i].name;
238 int board_early_init_f(void)
241 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
242 zynqmp_pmufw_version();
245 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
252 #define ZYNQMP_VERSION_SIZE 9
256 printf("EL Level:\tEL%d\n", current_el());
258 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
259 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
260 defined(CONFIG_SPL_BUILD))
261 if (current_el() != 3) {
262 static char version[ZYNQMP_VERSION_SIZE];
264 strncat(version, "zu", 2);
265 zynqmppl.name = strncat(version,
266 zynqmp_get_silicon_idcode_name(),
267 ZYNQMP_VERSION_SIZE - 3);
268 printf("Chip ID:\t%s\n", zynqmppl.name);
270 fpga_add(fpga_xilinx, &zynqmppl);
277 int board_early_init_r(void)
281 if (current_el() != 3)
284 val = readl(&crlapb_base->timestamp_ref_ctrl);
285 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
288 val = readl(&crlapb_base->timestamp_ref_ctrl);
289 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
290 writel(val, &crlapb_base->timestamp_ref_ctrl);
292 /* Program freq register in System counter */
293 writel(zynqmp_get_system_timer_freq(),
294 &iou_scntr_secure->base_frequency_id_register);
295 /* And enable system counter */
296 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
297 &iou_scntr_secure->counter_control_register);
302 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
304 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
305 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
306 defined(CONFIG_ZYNQ_EEPROM_BUS)
307 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
309 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
310 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
312 printf("I2C EEPROM MAC address read failed\n");
318 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
319 int dram_init_banksize(void)
321 return fdtdec_setup_memory_banksize();
326 if (fdtdec_setup_memory_size() != 0)
334 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
340 void reset_cpu(ulong addr)
344 int board_late_init(void)
353 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
354 debug("Saved variables - Skipping\n");
358 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
362 if (reg >> BOOT_MODE_ALT_SHIFT)
363 reg >>= BOOT_MODE_ALT_SHIFT;
365 bootmode = reg & BOOT_MODES_MASK;
372 env_set("modeboot", "usb_dfu_spl");
377 env_set("modeboot", "jtagboot");
379 case QSPI_MODE_24BIT:
380 case QSPI_MODE_32BIT:
383 env_set("modeboot", "qspiboot");
388 env_set("modeboot", "emmcboot");
393 env_set("modeboot", "sdboot");
400 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
402 env_set("sdbootdev", "1");
406 env_set("modeboot", "sdboot");
411 env_set("modeboot", "nandboot");
415 printf("Invalid Boot Mode:0x%x\n", bootmode);
420 * One terminating char + one byte for space between mode
421 * and default boot_targets
423 env_targets = env_get("boot_targets");
425 new_targets = calloc(1, strlen(mode) +
426 strlen(env_targets) + 2);
427 sprintf(new_targets, "%s %s", mode, env_targets);
429 new_targets = calloc(1, strlen(mode) + 2);
430 sprintf(new_targets, "%s", mode);
433 env_set("boot_targets", new_targets);
440 puts("Board: Xilinx ZynqMP\n");
444 #ifdef CONFIG_USB_DWC3
445 static struct dwc3_device dwc3_device_data0 = {
446 .maximum_speed = USB_SPEED_HIGH,
447 .base = ZYNQMP_USB0_XHCI_BASEADDR,
448 .dr_mode = USB_DR_MODE_PERIPHERAL,
452 static struct dwc3_device dwc3_device_data1 = {
453 .maximum_speed = USB_SPEED_HIGH,
454 .base = ZYNQMP_USB1_XHCI_BASEADDR,
455 .dr_mode = USB_DR_MODE_PERIPHERAL,
459 int usb_gadget_handle_interrupts(int index)
461 dwc3_uboot_handle_interrupt(index);
465 int board_usb_init(int index, enum usb_init_type init)
467 debug("%s: index %x\n", __func__, index);
469 #if defined(CONFIG_USB_GADGET_DOWNLOAD)
470 g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
475 return dwc3_uboot_init(&dwc3_device_data0);
477 return dwc3_uboot_init(&dwc3_device_data1);
483 int board_usb_cleanup(int index, enum usb_init_type init)
485 dwc3_uboot_exit(index);