2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clk.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/sys_proto.h>
17 #include <dwc3-uboot.h>
20 DECLARE_GLOBAL_DATA_PTR;
24 printf("EL Level:\tEL%d\n", current_el());
29 int board_early_init_r(void)
33 if (current_el() == 3) {
34 val = readl(&crlapb_base->timestamp_ref_ctrl);
35 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
36 writel(val, &crlapb_base->timestamp_ref_ctrl);
38 /* Program freq register in System counter */
39 writel(zynqmp_get_system_timer_freq(),
40 &iou_scntr_secure->base_frequency_id_register);
41 /* And enable system counter */
42 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
43 &iou_scntr_secure->counter_control_register);
45 /* Program freq register in System counter and enable system counter */
46 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
47 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
48 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
49 &iou_scntr->counter_control_register);
54 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
56 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
57 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
58 defined(CONFIG_ZYNQ_EEPROM_BUS)
59 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
61 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
62 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
64 printf("I2C EEPROM MAC address read failed\n");
70 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
72 * fdt_get_reg - Fill buffer by information from DT
74 static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
75 const u32 *cell, int n)
78 int parent_offset = fdt_parent_offset(fdt, nodeoffset);
79 int address_cells = fdt_address_cells(fdt, parent_offset);
80 int size_cells = fdt_size_cells(fdt, parent_offset);
85 debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
86 __func__, address_cells, size_cells, buf, cell);
88 /* Check memory bank setup */
89 banks = n % (address_cells + size_cells);
91 panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
92 n, address_cells, size_cells);
94 banks = n / (address_cells + size_cells);
96 for (b = 0; b < banks; b++) {
97 debug("%s: Bank #%d:\n", __func__, b);
98 if (address_cells == 2) {
102 val = fdt64_to_cpu(val);
103 debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
104 __func__, val, p, &cell[i]);
105 *(phys_addr_t *)p = val;
107 debug("%s: addr32=%x, ptr=%p\n",
108 __func__, fdt32_to_cpu(cell[i]), p);
109 *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
111 p += sizeof(phys_addr_t);
114 debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
115 sizeof(phys_addr_t));
117 if (size_cells == 2) {
121 vals = fdt64_to_cpu(vals);
123 debug("%s: size64=%llx, ptr=%p, cell=%p\n",
124 __func__, vals, p, &cell[i]);
125 *(phys_size_t *)p = vals;
127 debug("%s: size32=%x, ptr=%p\n",
128 __func__, fdt32_to_cpu(cell[i]), p);
129 *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
131 p += sizeof(phys_size_t);
134 debug("%s: ps=%p, i=%x, size=%zu\n",
135 __func__, p, i, sizeof(phys_size_t));
138 /* Return the first address size */
139 return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
142 #define FDT_REG_SIZE sizeof(u32)
143 /* Temp location for sharing data for storing */
144 /* Up to 64-bit address + 64-bit size */
145 static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
147 void dram_init_banksize(void)
151 memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
153 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
154 debug("Bank #%d: start %llx\n", bank,
155 (unsigned long long)gd->bd->bi_dram[bank].start);
156 debug("Bank #%d: size %llx\n", bank,
157 (unsigned long long)gd->bd->bi_dram[bank].size);
164 const void *blob = gd->fdt_blob;
167 memset(&tmp, 0, sizeof(tmp));
169 /* find or create "/memory" node. */
170 node = fdt_subnode_offset(blob, 0, "memory");
172 printf("%s: Can't get memory node\n", __func__);
176 /* Get pointer to cells and lenght of it */
177 cell = fdt_getprop(blob, node, "reg", &len);
179 printf("%s: Can't get reg property\n", __func__);
183 gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
185 debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
192 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
198 void reset_cpu(ulong addr)
202 #ifdef CONFIG_SCSI_AHCI_PLAT
205 #if defined(CONFIG_SATA_CEVA)
208 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
213 int board_late_init(void)
218 reg = readl(&crlapb_base->boot_mode);
219 bootmode = reg & BOOT_MODES_MASK;
225 setenv("modeboot", "jtagboot");
227 case QSPI_MODE_24BIT:
228 case QSPI_MODE_32BIT:
229 setenv("modeboot", "qspiboot");
234 setenv("modeboot", "sdboot");
238 setenv("modeboot", "sdboot");
242 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
243 setenv("sdbootdev", "1");
245 setenv("modeboot", "sdboot");
249 setenv("modeboot", "nandboot");
252 printf("Invalid Boot Mode:0x%x\n", bootmode);
261 puts("Board: Xilinx ZynqMP\n");
265 #ifdef CONFIG_USB_DWC3
266 static struct dwc3_device dwc3_device_data = {
267 .maximum_speed = USB_SPEED_HIGH,
268 .base = ZYNQMP_USB0_XHCI_BASEADDR,
269 .dr_mode = USB_DR_MODE_PERIPHERAL,
273 int usb_gadget_handle_interrupts(void)
275 dwc3_uboot_handle_interrupt(0);
279 int board_usb_init(int index, enum usb_init_type init)
281 return dwc3_uboot_init(&dwc3_device_data);
284 int board_usb_cleanup(int index, enum usb_init_type init)
286 dwc3_uboot_exit(index);