2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/sys_proto.h>
16 #include <dwc3-uboot.h>
18 DECLARE_GLOBAL_DATA_PTR;
22 printf("EL Level:\tEL%d\n", current_el());
27 int board_early_init_r(void)
31 val = readl(&crlapb_base->timestamp_ref_ctrl);
32 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
33 writel(val, &crlapb_base->timestamp_ref_ctrl);
35 /* Program freq register in System counter and enable system counter */
36 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
37 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
38 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
39 &iou_scntr->counter_control_register);
46 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
56 void reset_cpu(ulong addr)
60 #ifdef CONFIG_SCSI_AHCI_PLAT
63 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
68 int board_late_init(void)
73 reg = readl(&crlapb_base->boot_mode);
74 bootmode = reg & BOOT_MODES_MASK;
79 setenv("modeboot", "sdboot");
82 printf("Invalid Boot Mode:0x%x\n", bootmode);
91 puts("Board:\tXilinx ZynqMP\n");
95 #ifdef CONFIG_USB_DWC3
96 static struct dwc3_device dwc3_device_data = {
97 .maximum_speed = USB_SPEED_HIGH,
98 .base = ZYNQMP_USB0_XHCI_BASEADDR,
99 .dr_mode = USB_DR_MODE_PERIPHERAL,
103 int usb_gadget_handle_interrupts(void)
105 dwc3_uboot_handle_interrupt(0);
109 int board_usb_init(int index, enum usb_init_type init)
111 return dwc3_uboot_init(&dwc3_device_data);
114 int board_usb_cleanup(int index, enum usb_init_type init)
116 dwc3_uboot_exit(index);