board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <sata.h>
   9 #include <ahci.h>
  10 #include <scsi.h>
  11 #include <malloc.h>
  12 #include <wdt.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/psu_init_gpl.h>
  17 #include <asm/io.h>
  18 #include <dm/device.h>
  19 #include <dm/uclass.h>
  20 #include <usb.h>
  21 #include <dwc3-uboot.h>
  22 #include <zynqmppl.h>
  23 #include <i2c.h>
  24 #include <g_dnl.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
  29 static struct udevice *watchdog_dev;
  30 #endif
  31
  32 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  33     !defined(CONFIG_SPL_BUILD)
  34 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  35
  36 static const struct {
  37         u32 id;
  38         u32 ver;
  39         char *name;
  40         bool evexists;
  41 } zynqmp_devices[] = {
  42         {
  43                 .id = 0x10,
  44                 .name = "3eg",
  45         },
  46         {
  47                 .id = 0x10,
  48                 .ver = 0x2c,
  49                 .name = "3cg",
  50         },
  51         {
  52                 .id = 0x11,
  53                 .name = "2eg",
  54         },
  55         {
  56                 .id = 0x11,
  57                 .ver = 0x2c,
  58                 .name = "2cg",
  59         },
  60         {
  61                 .id = 0x20,
  62                 .name = "5ev",
  63                 .evexists = 1,
  64         },
  65         {
  66                 .id = 0x20,
  67                 .ver = 0x100,
  68                 .name = "5eg",
  69                 .evexists = 1,
  70         },
  71         {
  72                 .id = 0x20,
  73                 .ver = 0x12c,
  74                 .name = "5cg",
  75         },
  76         {
  77                 .id = 0x21,
  78                 .name = "4ev",
  79                 .evexists = 1,
  80         },
  81         {
  82                 .id = 0x21,
  83                 .ver = 0x100,
  84                 .name = "4eg",
  85                 .evexists = 1,
  86         },
  87         {
  88                 .id = 0x21,
  89                 .ver = 0x12c,
  90                 .name = "4cg",
  91         },
  92         {
  93                 .id = 0x30,
  94                 .name = "7ev",
  95                 .evexists = 1,
  96         },
  97         {
  98                 .id = 0x30,
  99                 .ver = 0x100,
 100                 .name = "7eg",
 101                 .evexists = 1,
 102         },
 103         {
 104                 .id = 0x30,
 105                 .ver = 0x12c,
 106                 .name = "7cg",
 107         },
 108         {
 109                 .id = 0x38,
 110                 .name = "9eg",
 111         },
 112         {
 113                 .id = 0x38,
 114                 .ver = 0x2c,
 115                 .name = "9cg",
 116         },
 117         {
 118                 .id = 0x39,
 119                 .name = "6eg",
 120         },
 121         {
 122                 .id = 0x39,
 123                 .ver = 0x2c,
 124                 .name = "6cg",
 125         },
 126         {
 127                 .id = 0x40,
 128                 .name = "11eg",
 129         },
 130         { /* For testing purpose only */
 131                 .id = 0x50,
 132                 .ver = 0x2c,
 133                 .name = "15cg",
 134         },
 135         {
 136                 .id = 0x50,
 137                 .name = "15eg",
 138         },
 139         {
 140                 .id = 0x58,
 141                 .name = "19eg",
 142         },
 143         {
 144                 .id = 0x59,
 145                 .name = "17eg",
 146         },
 147         {
 148                 .id = 0x61,
 149                 .name = "21dr",
 150         },
 151         {
 152                 .id = 0x63,
 153                 .name = "23dr",
 154         },
 155         {
 156                 .id = 0x65,
 157                 .name = "25dr",
 158         },
 159         {
 160                 .id = 0x64,
 161                 .name = "27dr",
 162         },
 163         {
 164                 .id = 0x60,
 165                 .name = "28dr",
 166         },
 167         {
 168                 .id = 0x62,
 169                 .name = "29dr",
 170         },
 171 };
 172 #endif
 173
 174 int chip_id(unsigned char id)
 175 {
 176         struct pt_regs regs;
 177         int val = -EINVAL;
 178
 179         if (current_el() != 3) {
 180                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 181                 regs.regs[1] = 0;
 182                 regs.regs[2] = 0;
 183                 regs.regs[3] = 0;
 184
 185                 smc_call(&regs);
 186
 187                 /*
 188                  * SMC returns:
 189                  * regs[0][31:0]  = status of the operation
 190                  * regs[0][63:32] = CSU.IDCODE register
 191                  * regs[1][31:0]  = CSU.version register
 192                  * regs[1][63:32] = CSU.IDCODE2 register
 193                  */
 194                 switch (id) {
 195                 case IDCODE:
 196                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 197                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 198                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 199                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 200                         val = regs.regs[0];
 201                         break;
 202                 case VERSION:
 203                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 204                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 205                         val = regs.regs[1];
 206                         break;
 207                 case IDCODE2:
 208                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 209                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 210                         val = regs.regs[1];
 211                         break;
 212                 default:
 213                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 214                 }
 215         } else {
 216                 switch (id) {
 217                 case IDCODE:
 218                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 219                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 220                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 221                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 222                         break;
 223                 case VERSION:
 224                         val = readl(ZYNQMP_CSU_VER_ADDR);
 225                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 226                         break;
 227                 default:
 228                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 229                 }
 230         }
 231
 232         return val;
 233 }
 234
 235 #define ZYNQMP_VERSION_SIZE             9
 236 #define ZYNQMP_PL_STATUS_BIT            9
 237 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 238 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 239
 240 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 241         !defined(CONFIG_SPL_BUILD)
 242 static char *zynqmp_get_silicon_idcode_name(void)
 243 {
 244         u32 i, id, ver;
 245         char *buf;
 246         static char name[ZYNQMP_VERSION_SIZE];
 247
 248         id = chip_id(IDCODE);
 249         ver = chip_id(IDCODE2);
 250
 251         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 252                 if ((zynqmp_devices[i].id == id) &&
 253                     (zynqmp_devices[i].ver == (ver &
 254                     ZYNQMP_CSU_VERSION_MASK))) {
 255                         strncat(name, "zu", 2);
 256                         strncat(name, zynqmp_devices[i].name,
 257                                 ZYNQMP_VERSION_SIZE - 3);
 258                         break;
 259                 }
 260         }
 261
 262         if (i >= ARRAY_SIZE(zynqmp_devices))
 263                 return "unknown";
 264
 265         if (!zynqmp_devices[i].evexists)
 266                 return name;
 267
 268         if (ver & ZYNQMP_PL_STATUS_MASK)
 269                 return name;
 270
 271         if (strstr(name, "eg") || strstr(name, "ev")) {
 272                 buf = strstr(name, "e");
 273                 *buf = '\0';
 274         }
 275
 276         return name;
 277 }
 278 #endif
 279
 280 int board_early_init_f(void)
 281 {
 282         int ret = 0;
 283 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 284         u32 pm_api_version;
 285
 286         pm_api_version = zynqmp_pmufw_version();
 287         printf("PMUFW:\tv%d.%d\n",
 288                pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 289                pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 290
 291         if (pm_api_version < ZYNQMP_PM_VERSION)
 292                 panic("PMUFW version error. Expected: v%d.%d\n",
 293                       ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 294 #endif
 295
 296 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 297         ret = psu_init();
 298 #endif
 299
 300 #if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
 301         /* bss is not cleared at time when watchdog_reset() is called */
 302         watchdog_dev = NULL;
 303 #endif
 304
 305         return ret;
 306 }
 307
 308 int board_init(void)
 309 {
 310         printf("EL Level:\tEL%d\n", current_el());
 311
 312 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 313     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 314     defined(CONFIG_SPL_BUILD))
 315         if (current_el() != 3) {
 316                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 317                 printf("Chip ID:\t%s\n", zynqmppl.name);
 318                 fpga_init();
 319                 fpga_add(fpga_xilinx, &zynqmppl);
 320         }
 321 #endif
 322
 323 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
 324         if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
 325                 debug("Watchdog: Not found by seq!\n");
 326                 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
 327                         puts("Watchdog: Not found!\n");
 328                         return 0;
 329                 }
 330         }
 331
 332         wdt_start(watchdog_dev, 0, 0);
 333         puts("Watchdog: Started\n");
 334 #endif
 335
 336         return 0;
 337 }
 338
 339 #ifdef CONFIG_WATCHDOG
 340 /* Called by macro WATCHDOG_RESET */
 341 void watchdog_reset(void)
 342 {
 343 # if !defined(CONFIG_SPL_BUILD)
 344         static ulong next_reset;
 345         ulong now;
 346
 347         if (!watchdog_dev)
 348                 return;
 349
 350         now = timer_get_us();
 351
 352         /* Do not reset the watchdog too often */
 353         if (now > next_reset) {
 354                 wdt_reset(watchdog_dev);
 355                 next_reset = now + 1000;
 356         }
 357 # endif
 358 }
 359 #endif
 360
 361 int board_early_init_r(void)
 362 {
 363         u32 val;
 364
 365         if (current_el() != 3)
 366                 return 0;
 367
 368         val = readl(&crlapb_base->timestamp_ref_ctrl);
 369         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 370
 371         if (!val) {
 372                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 373                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 374                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 375
 376                 /* Program freq register in System counter */
 377                 writel(zynqmp_get_system_timer_freq(),
 378                        &iou_scntr_secure->base_frequency_id_register);
 379                 /* And enable system counter */
 380                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 381                        &iou_scntr_secure->counter_control_register);
 382         }
 383         return 0;
 384 }
 385
 386 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 387 {
 388 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
 389     defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
 390     defined(CONFIG_ZYNQ_EEPROM_BUS)
 391         i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
 392
 393         if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
 394                         CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
 395                         ethaddr, 6))
 396                 printf("I2C EEPROM MAC address read failed\n");
 397 #endif
 398
 399         return 0;
 400 }
 401
 402 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 403                          char * const argv[])
 404 {
 405         int ret = 0;
 406
 407         if (current_el() > 1) {
 408                 smp_kick_all_cpus();
 409                 dcache_disable();
 410                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 411                                     ES_TO_AARCH64);
 412         } else {
 413                 printf("FAIL: current EL is not above EL1\n");
 414                 ret = EINVAL;
 415         }
 416         return ret;
 417 }
 418
 419 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 420 int dram_init_banksize(void)
 421 {
 422         int ret;
 423
 424         ret = fdtdec_setup_memory_banksize();
 425         if (ret)
 426                 return ret;
 427
 428         mem_map_fill();
 429
 430         return 0;
 431 }
 432
 433 int dram_init(void)
 434 {
 435         if (fdtdec_setup_mem_size_base() != 0)
 436                 return -EINVAL;
 437
 438         return 0;
 439 }
 440 #else
 441 int dram_init_banksize(void)
 442 {
 443 #if defined(CONFIG_NR_DRAM_BANKS)
 444         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 445         gd->bd->bi_dram[0].size = get_effective_memsize();
 446 #endif
 447
 448         mem_map_fill();
 449
 450         return 0;
 451 }
 452
 453 int dram_init(void)
 454 {
 455         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 456                                     CONFIG_SYS_SDRAM_SIZE);
 457
 458         return 0;
 459 }
 460 #endif
 461
 462 void reset_cpu(ulong addr)
 463 {
 464 }
 465
 466 static const struct {
 467         u32 bit;
 468         const char *name;
 469 } reset_reasons[] = {
 470         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 471         { RESET_REASON_SOFT, "SOFT" },
 472         { RESET_REASON_SRST, "SRST" },
 473         { RESET_REASON_PSONLY, "PS-ONLY" },
 474         { RESET_REASON_PMU, "PMU" },
 475         { RESET_REASON_INTERNAL, "INTERNAL" },
 476         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 477         {}
 478 };
 479
 480 static u32 reset_reason(void)
 481 {
 482         u32 ret;
 483         int i;
 484         const char *reason = NULL;
 485
 486         ret = readl(&crlapb_base->reset_reason);
 487
 488         puts("Reset reason:\t");
 489
 490         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 491                 if (ret & reset_reasons[i].bit) {
 492                         reason = reset_reasons[i].name;
 493                         printf("%s ", reset_reasons[i].name);
 494                         break;
 495                 }
 496         }
 497
 498         puts("\n");
 499
 500         env_set("reset_reason", reason);
 501
 502         writel(~0, &crlapb_base->reset_reason);
 503
 504         return ret;
 505 }
 506
 507 int board_late_init(void)
 508 {
 509         u32 reg = 0;
 510         u8 bootmode;
 511         struct udevice *dev;
 512         int bootseq = -1;
 513         int bootseq_len = 0;
 514         int env_targets_len = 0;
 515         const char *mode;
 516         char *new_targets;
 517         char *env_targets;
 518         int ret;
 519
 520         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 521                 debug("Saved variables - Skipping\n");
 522                 return 0;
 523         }
 524
 525         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 526         if (ret)
 527                 return -EINVAL;
 528
 529         if (reg >> BOOT_MODE_ALT_SHIFT)
 530                 reg >>= BOOT_MODE_ALT_SHIFT;
 531
 532         bootmode = reg & BOOT_MODES_MASK;
 533
 534         puts("Bootmode: ");
 535         switch (bootmode) {
 536         case USB_MODE:
 537                 puts("USB_MODE\n");
 538                 mode = "usb";
 539                 env_set("modeboot", "usb_dfu_spl");
 540                 break;
 541         case JTAG_MODE:
 542                 puts("JTAG_MODE\n");
 543                 mode = "pxe dhcp";
 544                 env_set("modeboot", "jtagboot");
 545                 break;
 546         case QSPI_MODE_24BIT:
 547         case QSPI_MODE_32BIT:
 548                 mode = "qspi0";
 549                 puts("QSPI_MODE\n");
 550                 env_set("modeboot", "qspiboot");
 551                 break;
 552         case EMMC_MODE:
 553                 puts("EMMC_MODE\n");
 554                 mode = "mmc0";
 555                 env_set("modeboot", "emmcboot");
 556                 break;
 557         case SD_MODE:
 558                 puts("SD_MODE\n");
 559                 if (uclass_get_device_by_name(UCLASS_MMC,
 560                                               "sdhci@ff160000", &dev)) {
 561                         puts("Boot from SD0 but without SD0 enabled!\n");
 562                         return -1;
 563                 }
 564                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 565
 566                 mode = "mmc";
 567                 bootseq = dev->seq;
 568                 env_set("modeboot", "sdboot");
 569                 break;
 570         case SD1_LSHFT_MODE:
 571                 puts("LVL_SHFT_");
 572                 /* fall through */
 573         case SD_MODE1:
 574                 puts("SD_MODE1\n");
 575                 if (uclass_get_device_by_name(UCLASS_MMC,
 576                                               "sdhci@ff170000", &dev)) {
 577                         puts("Boot from SD1 but without SD1 enabled!\n");
 578                         return -1;
 579                 }
 580                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 581
 582                 mode = "mmc";
 583                 bootseq = dev->seq;
 584                 env_set("modeboot", "sdboot");
 585                 break;
 586         case NAND_MODE:
 587                 puts("NAND_MODE\n");
 588                 mode = "nand0";
 589                 env_set("modeboot", "nandboot");
 590                 break;
 591         default:
 592                 mode = "";
 593                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 594                 break;
 595         }
 596
 597         if (bootseq >= 0) {
 598                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 599                 debug("Bootseq len: %x\n", bootseq_len);
 600         }
 601
 602         /*
 603          * One terminating char + one byte for space between mode
 604          * and default boot_targets
 605          */
 606         env_targets = env_get("boot_targets");
 607         if (env_targets)
 608                 env_targets_len = strlen(env_targets);
 609
 610         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 611                              bootseq_len);
 612         if (!new_targets)
 613                 return -ENOMEM;
 614
 615         if (bootseq >= 0)
 616                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 617                         env_targets ? env_targets : "");
 618         else
 619                 sprintf(new_targets, "%s %s", mode,
 620                         env_targets ? env_targets : "");
 621
 622         env_set("boot_targets", new_targets);
 623
 624         reset_reason();
 625
 626         return 0;
 627 }
 628
 629 int checkboard(void)
 630 {
 631         puts("Board: Xilinx ZynqMP\n");
 632         return 0;
 633 }