board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <debug_uart.h>
  11 #include <env.h>
  12 #include <env_internal.h>
  13 #include <init.h>
  14 #include <log.h>
  15 #include <net.h>
  16 #include <sata.h>
  17 #include <ahci.h>
  18 #include <scsi.h>
  19 #include <malloc.h>
  20 #include <wdt.h>
  21 #include <asm/arch/clk.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/psu_init_gpl.h>
  25 #include <asm/cache.h>
  26 #include <asm/io.h>
  27 #include <asm/ptrace.h>
  28 #include <dm/device.h>
  29 #include <dm/uclass.h>
  30 #include <usb.h>
  31 #include <dwc3-uboot.h>
  32 #include <zynqmppl.h>
  33 #include <zynqmp_firmware.h>
  34 #include <g_dnl.h>
  35 #include <linux/bitops.h>
  36 #include <linux/delay.h>
  37 #include <linux/sizes.h>
  38 #include "../common/board.h"
  39
  40 #include "pm_cfg_obj.h"
  41
  42 #define ZYNQMP_VERSION_SIZE     7
  43 #define EFUSE_VCU_DIS_MASK     0x100
  44 #define EFUSE_VCU_DIS_SHIFT    8
  45 #define EFUSE_GPU_DIS_MASK     0x20
  46 #define EFUSE_GPU_DIS_SHIFT    5
  47 #define IDCODE2_PL_INIT_MASK   0x200
  48 #define IDCODE2_PL_INIT_SHIFT  9
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
  53 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  54
  55 enum {
  56         ZYNQMP_VARIANT_EG = BIT(0U),
  57         ZYNQMP_VARIANT_EV = BIT(1U),
  58         ZYNQMP_VARIANT_CG = BIT(2U),
  59         ZYNQMP_VARIANT_DR = BIT(3U),
  60 };
  61
  62 static const struct {
  63         u32 id;
  64         u8 device;
  65         u8 variants;
  66 } zynqmp_devices[] = {
  67         {
  68                 .id = 0x04711093,
  69                 .device = 2,
  70                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  71         },
  72         {
  73                 .id = 0x04710093,
  74                 .device = 3,
  75                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  76         },
  77         {
  78                 .id = 0x04721093,
  79                 .device = 4,
  80                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  81                         ZYNQMP_VARIANT_EV,
  82         },
  83         {
  84                 .id = 0x04720093,
  85                 .device = 5,
  86                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  87                         ZYNQMP_VARIANT_EV,
  88         },
  89         {
  90                 .id = 0x04739093,
  91                 .device = 6,
  92                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  93         },
  94         {
  95                 .id = 0x04730093,
  96                 .device = 7,
  97                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  98                         ZYNQMP_VARIANT_EV,
  99         },
 100         {
 101                 .id = 0x04738093,
 102                 .device = 9,
 103                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 104         },
 105         {
 106                 .id = 0x04740093,
 107                 .device = 11,
 108                 .variants = ZYNQMP_VARIANT_EG,
 109         },
 110         {
 111                 .id = 0x04750093,
 112                 .device = 15,
 113                 .variants = ZYNQMP_VARIANT_EG,
 114         },
 115         {
 116                 .id = 0x04759093,
 117                 .device = 17,
 118                 .variants = ZYNQMP_VARIANT_EG,
 119         },
 120         {
 121                 .id = 0x04758093,
 122                 .device = 19,
 123                 .variants = ZYNQMP_VARIANT_EG,
 124         },
 125         {
 126                 .id = 0x047E1093,
 127                 .device = 21,
 128                 .variants = ZYNQMP_VARIANT_DR,
 129         },
 130         {
 131                 .id = 0x047E3093,
 132                 .device = 23,
 133                 .variants = ZYNQMP_VARIANT_DR,
 134         },
 135         {
 136                 .id = 0x047E5093,
 137                 .device = 25,
 138                 .variants = ZYNQMP_VARIANT_DR,
 139         },
 140         {
 141                 .id = 0x047E4093,
 142                 .device = 27,
 143                 .variants = ZYNQMP_VARIANT_DR,
 144         },
 145         {
 146                 .id = 0x047E0093,
 147                 .device = 28,
 148                 .variants = ZYNQMP_VARIANT_DR,
 149         },
 150         {
 151                 .id = 0x047E2093,
 152                 .device = 29,
 153                 .variants = ZYNQMP_VARIANT_DR,
 154         },
 155         {
 156                 .id = 0x047E6093,
 157                 .device = 39,
 158                 .variants = ZYNQMP_VARIANT_DR,
 159         },
 160         {
 161                 .id = 0x047FD093,
 162                 .device = 43,
 163                 .variants = ZYNQMP_VARIANT_DR,
 164         },
 165         {
 166                 .id = 0x047F8093,
 167                 .device = 46,
 168                 .variants = ZYNQMP_VARIANT_DR,
 169         },
 170         {
 171                 .id = 0x047FF093,
 172                 .device = 47,
 173                 .variants = ZYNQMP_VARIANT_DR,
 174         },
 175         {
 176                 .id = 0x047FB093,
 177                 .device = 48,
 178                 .variants = ZYNQMP_VARIANT_DR,
 179         },
 180         {
 181                 .id = 0x047FE093,
 182                 .device = 49,
 183                 .variants = ZYNQMP_VARIANT_DR,
 184         },
 185 };
 186
 187 static char *zynqmp_get_silicon_idcode_name(void)
 188 {
 189         u32 i;
 190         u32 idcode, idcode2;
 191         char name[ZYNQMP_VERSION_SIZE];
 192         u32 ret_payload[PAYLOAD_ARG_CNT];
 193
 194         xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
 195
 196         /*
 197          * Firmware returns:
 198          * payload[0][31:0]  = status of the operation
 199          * payload[1]] = IDCODE
 200          * payload[2][19:0]  = Version
 201          * payload[2][28:20] = EXTENDED_IDCODE
 202          * payload[2][29] = PL_INIT
 203          */
 204
 205         idcode  = ret_payload[1];
 206         idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 207         debug("%s, IDCODE: 0x%0X, IDCODE2: 0x%0X\r\n", __func__, idcode,
 208               idcode2);
 209
 210         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 211                 if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
 212                         break;
 213         }
 214
 215         if (i >= ARRAY_SIZE(zynqmp_devices))
 216                 return "unknown";
 217
 218         /* Add device prefix to the name */
 219         strncpy(name, "zu", ZYNQMP_VERSION_SIZE);
 220         strncat(&name[2], simple_itoa(zynqmp_devices[i].device), 2);
 221
 222         if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
 223                 /* Devices with EV variant might be EG/CG/EV family */
 224                 if (idcode2 & IDCODE2_PL_INIT_MASK) {
 225                         u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
 226                                       EFUSE_VCU_DIS_SHIFT) << 1 |
 227                                      ((idcode2 & EFUSE_GPU_DIS_MASK) >>
 228                                       EFUSE_GPU_DIS_SHIFT);
 229
 230                         /*
 231                          * Get family name based on extended idcode values as
 232                          * determined on UG1087, EXTENDED_IDCODE register
 233                          * description
 234                          */
 235                         switch (family) {
 236                         case 0x00:
 237                                 strncat(name, "ev", 2);
 238                                 break;
 239                         case 0x10:
 240                                 strncat(name, "eg", 2);
 241                                 break;
 242                         case 0x11:
 243                                 strncat(name, "cg", 2);
 244                                 break;
 245                         default:
 246                                 /* Do not append family name*/
 247                                 break;
 248                         }
 249                 } else {
 250                         /*
 251                          * When PL powered down the VCU Disable efuse cannot be
 252                          * read. So, ignore the bit and just findout if it is CG
 253                          * or EG/EV variant.
 254                          */
 255                         strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
 256                                 "e", 2);
 257                 }
 258         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
 259                 /* Devices with CG variant might be EG or CG family */
 260                 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
 261         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
 262                 strncat(name, "eg", 2);
 263         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
 264                 strncat(name, "dr", 2);
 265         } else {
 266                 debug("Variant not identified\n");
 267         }
 268
 269         return strdup(name);
 270 }
 271 #endif
 272
 273 int board_early_init_f(void)
 274 {
 275 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 276         int ret;
 277
 278         ret = psu_init();
 279         if (ret)
 280                 return ret;
 281
 282         /* Delay is required for clocks to be propagated */
 283         udelay(1000000);
 284 #endif
 285
 286 #ifdef CONFIG_DEBUG_UART
 287         /* Uart debug for sure */
 288         debug_uart_init();
 289         puts("Debug uart enabled\n"); /* or printch() */
 290 #endif
 291
 292         return 0;
 293 }
 294
 295 static int multi_boot(void)
 296 {
 297         u32 multiboot;
 298
 299         multiboot = readl(&csu_base->multi_boot);
 300
 301         printf("Multiboot:\t%d\n", multiboot);
 302
 303         return 0;
 304 }
 305
 306 #define PS_SYSMON_ANALOG_BUS_VAL        0x3210
 307 #define PS_SYSMON_ANALOG_BUS_REG        0xFFA50914
 308
 309 int board_init(void)
 310 {
 311 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 312         struct udevice *dev;
 313
 314         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 315         if (!dev)
 316                 panic("PMU Firmware device not found - Enable it");
 317 #endif
 318
 319 #if defined(CONFIG_SPL_BUILD)
 320         /* Check *at build time* if the filename is an non-empty string */
 321         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 322                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 323                                                 zynqmp_pm_cfg_obj_size);
 324 #endif
 325
 326         printf("EL Level:\tEL%d\n", current_el());
 327
 328         /* Bug in ROM sets wrong value in this register */
 329         writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
 330
 331 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 332         zynqmppl.name = zynqmp_get_silicon_idcode_name();
 333         printf("Chip ID:\t%s\n", zynqmppl.name);
 334         fpga_init();
 335         fpga_add(fpga_xilinx, &zynqmppl);
 336 #endif
 337
 338         if (current_el() == 3)
 339                 multi_boot();
 340
 341         return 0;
 342 }
 343
 344 int board_early_init_r(void)
 345 {
 346         u32 val;
 347
 348         if (current_el() != 3)
 349                 return 0;
 350
 351         val = readl(&crlapb_base->timestamp_ref_ctrl);
 352         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 353
 354         if (!val) {
 355                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 356                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 357                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 358
 359                 /* Program freq register in System counter */
 360                 writel(zynqmp_get_system_timer_freq(),
 361                        &iou_scntr_secure->base_frequency_id_register);
 362                 /* And enable system counter */
 363                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 364                        &iou_scntr_secure->counter_control_register);
 365         }
 366         return 0;
 367 }
 368
 369 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 370                          char *const argv[])
 371 {
 372         int ret = 0;
 373
 374         if (current_el() > 1) {
 375                 smp_kick_all_cpus();
 376                 dcache_disable();
 377                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 378                                     ES_TO_AARCH64);
 379         } else {
 380                 printf("FAIL: current EL is not above EL1\n");
 381                 ret = EINVAL;
 382         }
 383         return ret;
 384 }
 385
 386 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 387 int dram_init_banksize(void)
 388 {
 389         int ret;
 390
 391         ret = fdtdec_setup_memory_banksize();
 392         if (ret)
 393                 return ret;
 394
 395         mem_map_fill();
 396
 397         return 0;
 398 }
 399
 400 int dram_init(void)
 401 {
 402         if (fdtdec_setup_mem_size_base() != 0)
 403                 return -EINVAL;
 404
 405         return 0;
 406 }
 407 #else
 408 int dram_init_banksize(void)
 409 {
 410         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 411         gd->bd->bi_dram[0].size = get_effective_memsize();
 412
 413         mem_map_fill();
 414
 415         return 0;
 416 }
 417
 418 int dram_init(void)
 419 {
 420         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 421                                     CONFIG_SYS_SDRAM_SIZE);
 422
 423         return 0;
 424 }
 425 #endif
 426
 427 void reset_cpu(ulong addr)
 428 {
 429 }
 430
 431 static u8 __maybe_unused zynqmp_get_bootmode(void)
 432 {
 433         u8 bootmode;
 434         u32 reg = 0;
 435         int ret;
 436
 437         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 438         if (ret)
 439                 return -EINVAL;
 440
 441         if (reg >> BOOT_MODE_ALT_SHIFT)
 442                 reg >>= BOOT_MODE_ALT_SHIFT;
 443
 444         bootmode = reg & BOOT_MODES_MASK;
 445
 446         return bootmode;
 447 }
 448
 449 #if defined(CONFIG_BOARD_LATE_INIT)
 450 static const struct {
 451         u32 bit;
 452         const char *name;
 453 } reset_reasons[] = {
 454         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 455         { RESET_REASON_SOFT, "SOFT" },
 456         { RESET_REASON_SRST, "SRST" },
 457         { RESET_REASON_PSONLY, "PS-ONLY" },
 458         { RESET_REASON_PMU, "PMU" },
 459         { RESET_REASON_INTERNAL, "INTERNAL" },
 460         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 461         {}
 462 };
 463
 464 static int reset_reason(void)
 465 {
 466         u32 reg;
 467         int i, ret;
 468         const char *reason = NULL;
 469
 470         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 471         if (ret)
 472                 return -EINVAL;
 473
 474         puts("Reset reason:\t");
 475
 476         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 477                 if (reg & reset_reasons[i].bit) {
 478                         reason = reset_reasons[i].name;
 479                         printf("%s ", reset_reasons[i].name);
 480                         break;
 481                 }
 482         }
 483
 484         puts("\n");
 485
 486         env_set("reset_reason", reason);
 487
 488         ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
 489         if (ret)
 490                 return -EINVAL;
 491
 492         return ret;
 493 }
 494
 495 static int set_fdtfile(void)
 496 {
 497         char *compatible, *fdtfile;
 498         const char *suffix = ".dtb";
 499         const char *vendor = "xilinx/";
 500         int fdt_compat_len;
 501
 502         if (env_get("fdtfile"))
 503                 return 0;
 504
 505         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
 506                                          &fdt_compat_len);
 507         if (compatible && fdt_compat_len) {
 508                 char *name;
 509
 510                 debug("Compatible: %s\n", compatible);
 511
 512                 name = strchr(compatible, ',');
 513                 if (!name)
 514                         return -EINVAL;
 515
 516                 name++;
 517
 518                 fdtfile = calloc(1, strlen(vendor) + strlen(name) +
 519                                  strlen(suffix) + 1);
 520                 if (!fdtfile)
 521                         return -ENOMEM;
 522
 523                 sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
 524
 525                 env_set("fdtfile", fdtfile);
 526                 free(fdtfile);
 527         }
 528
 529         return 0;
 530 }
 531
 532 int board_late_init(void)
 533 {
 534         u8 bootmode;
 535         struct udevice *dev;
 536         int bootseq = -1;
 537         int bootseq_len = 0;
 538         int env_targets_len = 0;
 539         const char *mode;
 540         char *new_targets;
 541         char *env_targets;
 542         int ret;
 543
 544 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 545         usb_ether_init();
 546 #endif
 547
 548         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 549                 debug("Saved variables - Skipping\n");
 550                 return 0;
 551         }
 552
 553         if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
 554                 return 0;
 555
 556         ret = set_fdtfile();
 557         if (ret)
 558                 return ret;
 559
 560         bootmode = zynqmp_get_bootmode();
 561
 562         puts("Bootmode: ");
 563         switch (bootmode) {
 564         case USB_MODE:
 565                 puts("USB_MODE\n");
 566                 mode = "usb";
 567                 env_set("modeboot", "usb_dfu_spl");
 568                 break;
 569         case JTAG_MODE:
 570                 puts("JTAG_MODE\n");
 571                 mode = "jtag pxe dhcp";
 572                 env_set("modeboot", "jtagboot");
 573                 break;
 574         case QSPI_MODE_24BIT:
 575         case QSPI_MODE_32BIT:
 576                 mode = "qspi0";
 577                 puts("QSPI_MODE\n");
 578                 env_set("modeboot", "qspiboot");
 579                 break;
 580         case EMMC_MODE:
 581                 puts("EMMC_MODE\n");
 582                 if (uclass_get_device_by_name(UCLASS_MMC,
 583                                               "mmc@ff160000", &dev) &&
 584                     uclass_get_device_by_name(UCLASS_MMC,
 585                                               "sdhci@ff160000", &dev)) {
 586                         puts("Boot from EMMC but without SD0 enabled!\n");
 587                         return -1;
 588                 }
 589                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 590
 591                 mode = "mmc";
 592                 bootseq = dev->seq;
 593                 break;
 594         case SD_MODE:
 595                 puts("SD_MODE\n");
 596                 if (uclass_get_device_by_name(UCLASS_MMC,
 597                                               "mmc@ff160000", &dev) &&
 598                     uclass_get_device_by_name(UCLASS_MMC,
 599                                               "sdhci@ff160000", &dev)) {
 600                         puts("Boot from SD0 but without SD0 enabled!\n");
 601                         return -1;
 602                 }
 603                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 604
 605                 mode = "mmc";
 606                 bootseq = dev->seq;
 607                 env_set("modeboot", "sdboot");
 608                 break;
 609         case SD1_LSHFT_MODE:
 610                 puts("LVL_SHFT_");
 611                 /* fall through */
 612         case SD_MODE1:
 613                 puts("SD_MODE1\n");
 614                 if (uclass_get_device_by_name(UCLASS_MMC,
 615                                               "mmc@ff170000", &dev) &&
 616                     uclass_get_device_by_name(UCLASS_MMC,
 617                                               "sdhci@ff170000", &dev)) {
 618                         puts("Boot from SD1 but without SD1 enabled!\n");
 619                         return -1;
 620                 }
 621                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 622
 623                 mode = "mmc";
 624                 bootseq = dev->seq;
 625                 env_set("modeboot", "sdboot");
 626                 break;
 627         case NAND_MODE:
 628                 puts("NAND_MODE\n");
 629                 mode = "nand0";
 630                 env_set("modeboot", "nandboot");
 631                 break;
 632         default:
 633                 mode = "";
 634                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 635                 break;
 636         }
 637
 638         if (bootseq >= 0) {
 639                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 640                 debug("Bootseq len: %x\n", bootseq_len);
 641         }
 642
 643         /*
 644          * One terminating char + one byte for space between mode
 645          * and default boot_targets
 646          */
 647         env_targets = env_get("boot_targets");
 648         if (env_targets)
 649                 env_targets_len = strlen(env_targets);
 650
 651         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 652                              bootseq_len);
 653         if (!new_targets)
 654                 return -ENOMEM;
 655
 656         if (bootseq >= 0)
 657                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 658                         env_targets ? env_targets : "");
 659         else
 660                 sprintf(new_targets, "%s %s", mode,
 661                         env_targets ? env_targets : "");
 662
 663         env_set("boot_targets", new_targets);
 664
 665         reset_reason();
 666
 667         return board_late_init_xilinx();
 668 }
 669 #endif
 670
 671 int checkboard(void)
 672 {
 673         puts("Board: Xilinx ZynqMP\n");
 674         return 0;
 675 }
 676
 677 enum env_location env_get_location(enum env_operation op, int prio)
 678 {
 679         u32 bootmode = zynqmp_get_bootmode();
 680
 681         if (prio)
 682                 return ENVL_UNKNOWN;
 683
 684         switch (bootmode) {
 685         case EMMC_MODE:
 686         case SD_MODE:
 687         case SD1_LSHFT_MODE:
 688         case SD_MODE1:
 689                 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
 690                         return ENVL_FAT;
 691                 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
 692                         return ENVL_EXT4;
 693                 return ENVL_UNKNOWN;
 694         case NAND_MODE:
 695                 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
 696                         return ENVL_NAND;
 697                 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
 698                         return ENVL_UBI;
 699                 return ENVL_UNKNOWN;
 700         case QSPI_MODE_24BIT:
 701         case QSPI_MODE_32BIT:
 702                 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
 703                         return ENVL_SPI_FLASH;
 704                 return ENVL_UNKNOWN;
 705         case JTAG_MODE:
 706         default:
 707                 return ENVL_NOWHERE;
 708         }
 709 }