board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <sata.h>
   9 #include <ahci.h>
  10 #include <scsi.h>
  11 #include <malloc.h>
  12 #include <wdt.h>
  13 #include <asm/arch/clk.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/arch/psu_init_gpl.h>
  17 #include <asm/io.h>
  18 #include <dm/device.h>
  19 #include <dm/uclass.h>
  20 #include <usb.h>
  21 #include <dwc3-uboot.h>
  22 #include <zynqmppl.h>
  23 #include <g_dnl.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
  28 static struct udevice *watchdog_dev;
  29 #endif
  30
  31 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  32     !defined(CONFIG_SPL_BUILD)
  33 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  34
  35 static const struct {
  36         u32 id;
  37         u32 ver;
  38         char *name;
  39         bool evexists;
  40 } zynqmp_devices[] = {
  41         {
  42                 .id = 0x10,
  43                 .name = "3eg",
  44         },
  45         {
  46                 .id = 0x10,
  47                 .ver = 0x2c,
  48                 .name = "3cg",
  49         },
  50         {
  51                 .id = 0x11,
  52                 .name = "2eg",
  53         },
  54         {
  55                 .id = 0x11,
  56                 .ver = 0x2c,
  57                 .name = "2cg",
  58         },
  59         {
  60                 .id = 0x20,
  61                 .name = "5ev",
  62                 .evexists = 1,
  63         },
  64         {
  65                 .id = 0x20,
  66                 .ver = 0x100,
  67                 .name = "5eg",
  68                 .evexists = 1,
  69         },
  70         {
  71                 .id = 0x20,
  72                 .ver = 0x12c,
  73                 .name = "5cg",
  74                 .evexists = 1,
  75         },
  76         {
  77                 .id = 0x21,
  78                 .name = "4ev",
  79                 .evexists = 1,
  80         },
  81         {
  82                 .id = 0x21,
  83                 .ver = 0x100,
  84                 .name = "4eg",
  85                 .evexists = 1,
  86         },
  87         {
  88                 .id = 0x21,
  89                 .ver = 0x12c,
  90                 .name = "4cg",
  91                 .evexists = 1,
  92         },
  93         {
  94                 .id = 0x30,
  95                 .name = "7ev",
  96                 .evexists = 1,
  97         },
  98         {
  99                 .id = 0x30,
 100                 .ver = 0x100,
 101                 .name = "7eg",
 102                 .evexists = 1,
 103         },
 104         {
 105                 .id = 0x30,
 106                 .ver = 0x12c,
 107                 .name = "7cg",
 108                 .evexists = 1,
 109         },
 110         {
 111                 .id = 0x38,
 112                 .name = "9eg",
 113         },
 114         {
 115                 .id = 0x38,
 116                 .ver = 0x2c,
 117                 .name = "9cg",
 118         },
 119         {
 120                 .id = 0x39,
 121                 .name = "6eg",
 122         },
 123         {
 124                 .id = 0x39,
 125                 .ver = 0x2c,
 126                 .name = "6cg",
 127         },
 128         {
 129                 .id = 0x40,
 130                 .name = "11eg",
 131         },
 132         { /* For testing purpose only */
 133                 .id = 0x50,
 134                 .ver = 0x2c,
 135                 .name = "15cg",
 136         },
 137         {
 138                 .id = 0x50,
 139                 .name = "15eg",
 140         },
 141         {
 142                 .id = 0x58,
 143                 .name = "19eg",
 144         },
 145         {
 146                 .id = 0x59,
 147                 .name = "17eg",
 148         },
 149         {
 150                 .id = 0x61,
 151                 .name = "21dr",
 152         },
 153         {
 154                 .id = 0x63,
 155                 .name = "23dr",
 156         },
 157         {
 158                 .id = 0x65,
 159                 .name = "25dr",
 160         },
 161         {
 162                 .id = 0x64,
 163                 .name = "27dr",
 164         },
 165         {
 166                 .id = 0x60,
 167                 .name = "28dr",
 168         },
 169         {
 170                 .id = 0x62,
 171                 .name = "29dr",
 172         },
 173 };
 174 #endif
 175
 176 int chip_id(unsigned char id)
 177 {
 178         struct pt_regs regs;
 179         int val = -EINVAL;
 180
 181         if (current_el() != 3) {
 182                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 183                 regs.regs[1] = 0;
 184                 regs.regs[2] = 0;
 185                 regs.regs[3] = 0;
 186
 187                 smc_call(&regs);
 188
 189                 /*
 190                  * SMC returns:
 191                  * regs[0][31:0]  = status of the operation
 192                  * regs[0][63:32] = CSU.IDCODE register
 193                  * regs[1][31:0]  = CSU.version register
 194                  * regs[1][63:32] = CSU.IDCODE2 register
 195                  */
 196                 switch (id) {
 197                 case IDCODE:
 198                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 199                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 200                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 201                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 202                         val = regs.regs[0];
 203                         break;
 204                 case VERSION:
 205                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 206                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 207                         val = regs.regs[1];
 208                         break;
 209                 case IDCODE2:
 210                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 211                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 212                         val = regs.regs[1];
 213                         break;
 214                 default:
 215                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 216                 }
 217         } else {
 218                 switch (id) {
 219                 case IDCODE:
 220                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 221                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 222                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 223                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 224                         break;
 225                 case VERSION:
 226                         val = readl(ZYNQMP_CSU_VER_ADDR);
 227                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 228                         break;
 229                 default:
 230                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 231                 }
 232         }
 233
 234         return val;
 235 }
 236
 237 #define ZYNQMP_VERSION_SIZE             9
 238 #define ZYNQMP_PL_STATUS_BIT            9
 239 #define ZYNQMP_IPDIS_VCU_BIT            8
 240 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 241 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 242 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 243                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 244 #define MAX_VARIANTS_EV                 3
 245
 246 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 247         !defined(CONFIG_SPL_BUILD)
 248 static char *zynqmp_get_silicon_idcode_name(void)
 249 {
 250         u32 i, id, ver, j;
 251         char *buf;
 252         static char name[ZYNQMP_VERSION_SIZE];
 253
 254         id = chip_id(IDCODE);
 255         ver = chip_id(IDCODE2);
 256
 257         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 258                 if (zynqmp_devices[i].id == id) {
 259                         if (zynqmp_devices[i].evexists &&
 260                             !(ver & ZYNQMP_PL_STATUS_MASK))
 261                                 break;
 262                         if (zynqmp_devices[i].ver == (ver &
 263                             ZYNQMP_CSU_VERSION_MASK))
 264                                 break;
 265                 }
 266         }
 267
 268         if (i >= ARRAY_SIZE(zynqmp_devices))
 269                 return "unknown";
 270
 271         strncat(name, "zu", 2);
 272         if (!zynqmp_devices[i].evexists ||
 273             (ver & ZYNQMP_PL_STATUS_MASK)) {
 274                 strncat(name, zynqmp_devices[i].name,
 275                         ZYNQMP_VERSION_SIZE - 3);
 276                 return name;
 277         }
 278
 279         /*
 280          * Here we are means, PL not powered up and ev variant
 281          * exists. So, we need to ignore VCU disable bit(8) in
 282          * version and findout if its CG or EG/EV variant.
 283          */
 284         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 285                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 286                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 287                         strncat(name, zynqmp_devices[i].name,
 288                                 ZYNQMP_VERSION_SIZE - 3);
 289                         break;
 290                 }
 291         }
 292
 293         if (j >= MAX_VARIANTS_EV)
 294                 return "unknown";
 295
 296         if (strstr(name, "eg") || strstr(name, "ev")) {
 297                 buf = strstr(name, "e");
 298                 *buf = '\0';
 299         }
 300
 301         return name;
 302 }
 303 #endif
 304
 305 int board_early_init_f(void)
 306 {
 307         int ret = 0;
 308 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
 309         u32 pm_api_version;
 310
 311         pm_api_version = zynqmp_pmufw_version();
 312         printf("PMUFW:\tv%d.%d\n",
 313                pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 314                pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 315
 316         if (pm_api_version < ZYNQMP_PM_VERSION)
 317                 panic("PMUFW version error. Expected: v%d.%d\n",
 318                       ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 319 #endif
 320
 321 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 322         ret = psu_init();
 323 #endif
 324
 325 #if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
 326         /* bss is not cleared at time when watchdog_reset() is called */
 327         watchdog_dev = NULL;
 328 #endif
 329
 330         return ret;
 331 }
 332
 333 int board_init(void)
 334 {
 335         printf("EL Level:\tEL%d\n", current_el());
 336
 337 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 338     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 339     defined(CONFIG_SPL_BUILD))
 340         if (current_el() != 3) {
 341                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 342                 printf("Chip ID:\t%s\n", zynqmppl.name);
 343                 fpga_init();
 344                 fpga_add(fpga_xilinx, &zynqmppl);
 345         }
 346 #endif
 347
 348 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
 349         if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
 350                 debug("Watchdog: Not found by seq!\n");
 351                 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
 352                         puts("Watchdog: Not found!\n");
 353                         return 0;
 354                 }
 355         }
 356
 357         wdt_start(watchdog_dev, 0, 0);
 358         puts("Watchdog: Started\n");
 359 #endif
 360
 361         return 0;
 362 }
 363
 364 #ifdef CONFIG_WATCHDOG
 365 /* Called by macro WATCHDOG_RESET */
 366 void watchdog_reset(void)
 367 {
 368 # if !defined(CONFIG_SPL_BUILD)
 369         static ulong next_reset;
 370         ulong now;
 371
 372         if (!watchdog_dev)
 373                 return;
 374
 375         now = timer_get_us();
 376
 377         /* Do not reset the watchdog too often */
 378         if (now > next_reset) {
 379                 wdt_reset(watchdog_dev);
 380                 next_reset = now + 1000;
 381         }
 382 # endif
 383 }
 384 #endif
 385
 386 int board_early_init_r(void)
 387 {
 388         u32 val;
 389
 390         if (current_el() != 3)
 391                 return 0;
 392
 393         val = readl(&crlapb_base->timestamp_ref_ctrl);
 394         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 395
 396         if (!val) {
 397                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 398                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 399                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 400
 401                 /* Program freq register in System counter */
 402                 writel(zynqmp_get_system_timer_freq(),
 403                        &iou_scntr_secure->base_frequency_id_register);
 404                 /* And enable system counter */
 405                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 406                        &iou_scntr_secure->counter_control_register);
 407         }
 408         return 0;
 409 }
 410
 411 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 412                          char * const argv[])
 413 {
 414         int ret = 0;
 415
 416         if (current_el() > 1) {
 417                 smp_kick_all_cpus();
 418                 dcache_disable();
 419                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 420                                     ES_TO_AARCH64);
 421         } else {
 422                 printf("FAIL: current EL is not above EL1\n");
 423                 ret = EINVAL;
 424         }
 425         return ret;
 426 }
 427
 428 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 429 int dram_init_banksize(void)
 430 {
 431         int ret;
 432
 433         ret = fdtdec_setup_memory_banksize();
 434         if (ret)
 435                 return ret;
 436
 437         mem_map_fill();
 438
 439         return 0;
 440 }
 441
 442 int dram_init(void)
 443 {
 444         if (fdtdec_setup_mem_size_base() != 0)
 445                 return -EINVAL;
 446
 447         return 0;
 448 }
 449 #else
 450 int dram_init_banksize(void)
 451 {
 452 #if defined(CONFIG_NR_DRAM_BANKS)
 453         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 454         gd->bd->bi_dram[0].size = get_effective_memsize();
 455 #endif
 456
 457         mem_map_fill();
 458
 459         return 0;
 460 }
 461
 462 int dram_init(void)
 463 {
 464         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 465                                     CONFIG_SYS_SDRAM_SIZE);
 466
 467         return 0;
 468 }
 469 #endif
 470
 471 void reset_cpu(ulong addr)
 472 {
 473 }
 474
 475 #if defined(CONFIG_BOARD_LATE_INIT)
 476 static const struct {
 477         u32 bit;
 478         const char *name;
 479 } reset_reasons[] = {
 480         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 481         { RESET_REASON_SOFT, "SOFT" },
 482         { RESET_REASON_SRST, "SRST" },
 483         { RESET_REASON_PSONLY, "PS-ONLY" },
 484         { RESET_REASON_PMU, "PMU" },
 485         { RESET_REASON_INTERNAL, "INTERNAL" },
 486         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 487         {}
 488 };
 489
 490 static u32 reset_reason(void)
 491 {
 492         u32 ret;
 493         int i;
 494         const char *reason = NULL;
 495
 496         ret = readl(&crlapb_base->reset_reason);
 497
 498         puts("Reset reason:\t");
 499
 500         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 501                 if (ret & reset_reasons[i].bit) {
 502                         reason = reset_reasons[i].name;
 503                         printf("%s ", reset_reasons[i].name);
 504                         break;
 505                 }
 506         }
 507
 508         puts("\n");
 509
 510         env_set("reset_reason", reason);
 511
 512         writel(~0, &crlapb_base->reset_reason);
 513
 514         return ret;
 515 }
 516
 517 static int set_fdtfile(void)
 518 {
 519         char *compatible, *fdtfile;
 520         const char *suffix = ".dtb";
 521         const char *vendor = "xilinx/";
 522
 523         if (env_get("fdtfile"))
 524                 return 0;
 525
 526         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 527         if (compatible) {
 528                 debug("Compatible: %s\n", compatible);
 529
 530                 /* Discard vendor prefix */
 531                 strsep(&compatible, ",");
 532
 533                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 534                                  strlen(suffix) + 1);
 535                 if (!fdtfile)
 536                         return -ENOMEM;
 537
 538                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 539
 540                 env_set("fdtfile", fdtfile);
 541                 free(fdtfile);
 542         }
 543
 544         return 0;
 545 }
 546
 547 int board_late_init(void)
 548 {
 549         u32 reg = 0;
 550         u8 bootmode;
 551         struct udevice *dev;
 552         int bootseq = -1;
 553         int bootseq_len = 0;
 554         int env_targets_len = 0;
 555         const char *mode;
 556         char *new_targets;
 557         char *env_targets;
 558         int ret;
 559
 560 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 561         usb_ether_init();
 562 #endif
 563
 564         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 565                 debug("Saved variables - Skipping\n");
 566                 return 0;
 567         }
 568
 569         ret = set_fdtfile();
 570         if (ret)
 571                 return ret;
 572
 573         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 574         if (ret)
 575                 return -EINVAL;
 576
 577         if (reg >> BOOT_MODE_ALT_SHIFT)
 578                 reg >>= BOOT_MODE_ALT_SHIFT;
 579
 580         bootmode = reg & BOOT_MODES_MASK;
 581
 582         puts("Bootmode: ");
 583         switch (bootmode) {
 584         case USB_MODE:
 585                 puts("USB_MODE\n");
 586                 mode = "usb";
 587                 env_set("modeboot", "usb_dfu_spl");
 588                 break;
 589         case JTAG_MODE:
 590                 puts("JTAG_MODE\n");
 591                 mode = "pxe dhcp";
 592                 env_set("modeboot", "jtagboot");
 593                 break;
 594         case QSPI_MODE_24BIT:
 595         case QSPI_MODE_32BIT:
 596                 mode = "qspi0";
 597                 puts("QSPI_MODE\n");
 598                 env_set("modeboot", "qspiboot");
 599                 break;
 600         case EMMC_MODE:
 601                 puts("EMMC_MODE\n");
 602                 mode = "mmc0";
 603                 env_set("modeboot", "emmcboot");
 604                 break;
 605         case SD_MODE:
 606                 puts("SD_MODE\n");
 607                 if (uclass_get_device_by_name(UCLASS_MMC,
 608                                               "mmc@ff160000", &dev) &&
 609                     uclass_get_device_by_name(UCLASS_MMC,
 610                                               "sdhci@ff160000", &dev)) {
 611                         puts("Boot from SD0 but without SD0 enabled!\n");
 612                         return -1;
 613                 }
 614                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 615
 616                 mode = "mmc";
 617                 bootseq = dev->seq;
 618                 env_set("modeboot", "sdboot");
 619                 break;
 620         case SD1_LSHFT_MODE:
 621                 puts("LVL_SHFT_");
 622                 /* fall through */
 623         case SD_MODE1:
 624                 puts("SD_MODE1\n");
 625                 if (uclass_get_device_by_name(UCLASS_MMC,
 626                                               "mmc@ff170000", &dev) &&
 627                     uclass_get_device_by_name(UCLASS_MMC,
 628                                               "sdhci@ff170000", &dev)) {
 629                         puts("Boot from SD1 but without SD1 enabled!\n");
 630                         return -1;
 631                 }
 632                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 633
 634                 mode = "mmc";
 635                 bootseq = dev->seq;
 636                 env_set("modeboot", "sdboot");
 637                 break;
 638         case NAND_MODE:
 639                 puts("NAND_MODE\n");
 640                 mode = "nand0";
 641                 env_set("modeboot", "nandboot");
 642                 break;
 643         default:
 644                 mode = "";
 645                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 646                 break;
 647         }
 648
 649         if (bootseq >= 0) {
 650                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 651                 debug("Bootseq len: %x\n", bootseq_len);
 652         }
 653
 654         /*
 655          * One terminating char + one byte for space between mode
 656          * and default boot_targets
 657          */
 658         env_targets = env_get("boot_targets");
 659         if (env_targets)
 660                 env_targets_len = strlen(env_targets);
 661
 662         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 663                              bootseq_len);
 664         if (!new_targets)
 665                 return -ENOMEM;
 666
 667         if (bootseq >= 0)
 668                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 669                         env_targets ? env_targets : "");
 670         else
 671                 sprintf(new_targets, "%s %s", mode,
 672                         env_targets ? env_targets : "");
 673
 674         env_set("boot_targets", new_targets);
 675
 676         reset_reason();
 677
 678         return 0;
 679 }
 680 #endif
 681
 682 int checkboard(void)
 683 {
 684         puts("Board: Xilinx ZynqMP\n");
 685         return 0;
 686 }