board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <debug_uart.h>
  11 #include <env.h>
  12 #include <env_internal.h>
  13 #include <init.h>
  14 #include <log.h>
  15 #include <net.h>
  16 #include <sata.h>
  17 #include <ahci.h>
  18 #include <scsi.h>
  19 #include <malloc.h>
  20 #include <wdt.h>
  21 #include <asm/arch/clk.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/psu_init_gpl.h>
  25 #include <asm/cache.h>
  26 #include <asm/io.h>
  27 #include <asm/ptrace.h>
  28 #include <dm/device.h>
  29 #include <dm/uclass.h>
  30 #include <usb.h>
  31 #include <dwc3-uboot.h>
  32 #include <zynqmppl.h>
  33 #include <zynqmp_firmware.h>
  34 #include <g_dnl.h>
  35 #include <linux/bitops.h>
  36 #include <linux/delay.h>
  37 #include <linux/sizes.h>
  38 #include "../common/board.h"
  39
  40 #include "pm_cfg_obj.h"
  41
  42 #define ZYNQMP_VERSION_SIZE     7
  43 #define EFUSE_VCU_DIS_MASK      0x100
  44 #define EFUSE_VCU_DIS_SHIFT     8
  45 #define EFUSE_GPU_DIS_MASK      0x20
  46 #define EFUSE_GPU_DIS_SHIFT     5
  47 #define IDCODE2_PL_INIT_MASK    0x200
  48 #define IDCODE2_PL_INIT_SHIFT   9
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
  53 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  54
  55 enum {
  56         ZYNQMP_VARIANT_EG = BIT(0U),
  57         ZYNQMP_VARIANT_EV = BIT(1U),
  58         ZYNQMP_VARIANT_CG = BIT(2U),
  59         ZYNQMP_VARIANT_DR = BIT(3U),
  60 };
  61
  62 static const struct {
  63         u32 id;
  64         u8 device;
  65         u8 variants;
  66 } zynqmp_devices[] = {
  67         {
  68                 .id = 0x04711093,
  69                 .device = 2,
  70                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  71         },
  72         {
  73                 .id = 0x04710093,
  74                 .device = 3,
  75                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  76         },
  77         {
  78                 .id = 0x04721093,
  79                 .device = 4,
  80                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  81                         ZYNQMP_VARIANT_EV,
  82         },
  83         {
  84                 .id = 0x04720093,
  85                 .device = 5,
  86                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  87                         ZYNQMP_VARIANT_EV,
  88         },
  89         {
  90                 .id = 0x04739093,
  91                 .device = 6,
  92                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  93         },
  94         {
  95                 .id = 0x04730093,
  96                 .device = 7,
  97                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  98                         ZYNQMP_VARIANT_EV,
  99         },
 100         {
 101                 .id = 0x04738093,
 102                 .device = 9,
 103                 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
 104         },
 105         {
 106                 .id = 0x04740093,
 107                 .device = 11,
 108                 .variants = ZYNQMP_VARIANT_EG,
 109         },
 110         {
 111                 .id = 0x04750093,
 112                 .device = 15,
 113                 .variants = ZYNQMP_VARIANT_EG,
 114         },
 115         {
 116                 .id = 0x04759093,
 117                 .device = 17,
 118                 .variants = ZYNQMP_VARIANT_EG,
 119         },
 120         {
 121                 .id = 0x04758093,
 122                 .device = 19,
 123                 .variants = ZYNQMP_VARIANT_EG,
 124         },
 125         {
 126                 .id = 0x047E1093,
 127                 .device = 21,
 128                 .variants = ZYNQMP_VARIANT_DR,
 129         },
 130         {
 131                 .id = 0x047E3093,
 132                 .device = 23,
 133                 .variants = ZYNQMP_VARIANT_DR,
 134         },
 135         {
 136                 .id = 0x047E5093,
 137                 .device = 25,
 138                 .variants = ZYNQMP_VARIANT_DR,
 139         },
 140         {
 141                 .id = 0x047E4093,
 142                 .device = 27,
 143                 .variants = ZYNQMP_VARIANT_DR,
 144         },
 145         {
 146                 .id = 0x047E0093,
 147                 .device = 28,
 148                 .variants = ZYNQMP_VARIANT_DR,
 149         },
 150         {
 151                 .id = 0x047E2093,
 152                 .device = 29,
 153                 .variants = ZYNQMP_VARIANT_DR,
 154         },
 155         {
 156                 .id = 0x047E6093,
 157                 .device = 39,
 158                 .variants = ZYNQMP_VARIANT_DR,
 159         },
 160         {
 161                 .id = 0x047FD093,
 162                 .device = 43,
 163                 .variants = ZYNQMP_VARIANT_DR,
 164         },
 165         {
 166                 .id = 0x047F8093,
 167                 .device = 46,
 168                 .variants = ZYNQMP_VARIANT_DR,
 169         },
 170         {
 171                 .id = 0x047FF093,
 172                 .device = 47,
 173                 .variants = ZYNQMP_VARIANT_DR,
 174         },
 175         {
 176                 .id = 0x047FB093,
 177                 .device = 48,
 178                 .variants = ZYNQMP_VARIANT_DR,
 179         },
 180         {
 181                 .id = 0x047FE093,
 182                 .device = 49,
 183                 .variants = ZYNQMP_VARIANT_DR,
 184         },
 185 };
 186
 187 static char *zynqmp_get_silicon_idcode_name(void)
 188 {
 189         u32 i;
 190         u32 idcode, idcode2;
 191         char name[ZYNQMP_VERSION_SIZE];
 192         u32 ret_payload[PAYLOAD_ARG_CNT];
 193         int ret;
 194
 195         ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
 196         if (ret) {
 197                 debug("%s: Getting chipid failed\n", __func__);
 198                 return "unknown";
 199         }
 200
 201         /*
 202          * Firmware returns:
 203          * payload[0][31:0]  = status of the operation
 204          * payload[1]] = IDCODE
 205          * payload[2][19:0]  = Version
 206          * payload[2][28:20] = EXTENDED_IDCODE
 207          * payload[2][29] = PL_INIT
 208          */
 209
 210         idcode  = ret_payload[1];
 211         idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 212         debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
 213               idcode2);
 214
 215         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 216                 if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
 217                         break;
 218         }
 219
 220         if (i >= ARRAY_SIZE(zynqmp_devices))
 221                 return "unknown";
 222
 223         /* Add device prefix to the name */
 224         ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
 225                        zynqmp_devices[i].device);
 226         if (ret < 0)
 227                 return "unknown";
 228
 229         if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
 230                 /* Devices with EV variant might be EG/CG/EV family */
 231                 if (idcode2 & IDCODE2_PL_INIT_MASK) {
 232                         u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
 233                                       EFUSE_VCU_DIS_SHIFT) << 1 |
 234                                      ((idcode2 & EFUSE_GPU_DIS_MASK) >>
 235                                       EFUSE_GPU_DIS_SHIFT);
 236
 237                         /*
 238                          * Get family name based on extended idcode values as
 239                          * determined on UG1087, EXTENDED_IDCODE register
 240                          * description
 241                          */
 242                         switch (family) {
 243                         case 0x00:
 244                                 strncat(name, "ev", 2);
 245                                 break;
 246                         case 0x10:
 247                                 strncat(name, "eg", 2);
 248                                 break;
 249                         case 0x11:
 250                                 strncat(name, "cg", 2);
 251                                 break;
 252                         default:
 253                                 /* Do not append family name*/
 254                                 break;
 255                         }
 256                 } else {
 257                         /*
 258                          * When PL powered down the VCU Disable efuse cannot be
 259                          * read. So, ignore the bit and just findout if it is CG
 260                          * or EG/EV variant.
 261                          */
 262                         strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
 263                                 "e", 2);
 264                 }
 265         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
 266                 /* Devices with CG variant might be EG or CG family */
 267                 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
 268         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
 269                 strncat(name, "eg", 2);
 270         } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
 271                 strncat(name, "dr", 2);
 272         } else {
 273                 debug("Variant not identified\n");
 274         }
 275
 276         return strdup(name);
 277 }
 278 #endif
 279
 280 int board_early_init_f(void)
 281 {
 282 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 283         int ret;
 284
 285         ret = psu_init();
 286         if (ret)
 287                 return ret;
 288
 289         /* Delay is required for clocks to be propagated */
 290         udelay(1000000);
 291 #endif
 292
 293 #ifdef CONFIG_DEBUG_UART
 294         /* Uart debug for sure */
 295         debug_uart_init();
 296         puts("Debug uart enabled\n"); /* or printch() */
 297 #endif
 298
 299         return 0;
 300 }
 301
 302 static int multi_boot(void)
 303 {
 304         u32 multiboot;
 305
 306         multiboot = readl(&csu_base->multi_boot);
 307
 308         printf("Multiboot:\t%d\n", multiboot);
 309
 310         return 0;
 311 }
 312
 313 #define PS_SYSMON_ANALOG_BUS_VAL        0x3210
 314 #define PS_SYSMON_ANALOG_BUS_REG        0xFFA50914
 315
 316 int board_init(void)
 317 {
 318 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 319         struct udevice *dev;
 320
 321         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 322         if (!dev)
 323                 panic("PMU Firmware device not found - Enable it");
 324 #endif
 325
 326 #if defined(CONFIG_SPL_BUILD)
 327         /* Check *at build time* if the filename is an non-empty string */
 328         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 329                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 330                                                 zynqmp_pm_cfg_obj_size);
 331 #else
 332         if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
 333                 xilinx_read_eeprom();
 334 #endif
 335
 336         printf("EL Level:\tEL%d\n", current_el());
 337
 338         /* Bug in ROM sets wrong value in this register */
 339         writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
 340
 341 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 342         zynqmppl.name = zynqmp_get_silicon_idcode_name();
 343         printf("Chip ID:\t%s\n", zynqmppl.name);
 344         fpga_init();
 345         fpga_add(fpga_xilinx, &zynqmppl);
 346 #endif
 347
 348         if (current_el() == 3)
 349                 multi_boot();
 350
 351         return 0;
 352 }
 353
 354 int board_early_init_r(void)
 355 {
 356         u32 val;
 357
 358         if (current_el() != 3)
 359                 return 0;
 360
 361         val = readl(&crlapb_base->timestamp_ref_ctrl);
 362         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 363
 364         if (!val) {
 365                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 366                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 367                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 368
 369                 /* Program freq register in System counter */
 370                 writel(zynqmp_get_system_timer_freq(),
 371                        &iou_scntr_secure->base_frequency_id_register);
 372                 /* And enable system counter */
 373                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 374                        &iou_scntr_secure->counter_control_register);
 375         }
 376         return 0;
 377 }
 378
 379 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 380                          char *const argv[])
 381 {
 382         int ret = 0;
 383
 384         if (current_el() > 1) {
 385                 smp_kick_all_cpus();
 386                 dcache_disable();
 387                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 388                                     ES_TO_AARCH64);
 389         } else {
 390                 printf("FAIL: current EL is not above EL1\n");
 391                 ret = EINVAL;
 392         }
 393         return ret;
 394 }
 395
 396 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 397 int dram_init_banksize(void)
 398 {
 399         int ret;
 400
 401         ret = fdtdec_setup_memory_banksize();
 402         if (ret)
 403                 return ret;
 404
 405         mem_map_fill();
 406
 407         return 0;
 408 }
 409
 410 int dram_init(void)
 411 {
 412         if (fdtdec_setup_mem_size_base() != 0)
 413                 return -EINVAL;
 414
 415         return 0;
 416 }
 417 #else
 418 int dram_init_banksize(void)
 419 {
 420         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 421         gd->bd->bi_dram[0].size = get_effective_memsize();
 422
 423         mem_map_fill();
 424
 425         return 0;
 426 }
 427
 428 int dram_init(void)
 429 {
 430         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 431                                     CONFIG_SYS_SDRAM_SIZE);
 432
 433         return 0;
 434 }
 435 #endif
 436
 437 void reset_cpu(ulong addr)
 438 {
 439 }
 440
 441 static u8 __maybe_unused zynqmp_get_bootmode(void)
 442 {
 443         u8 bootmode;
 444         u32 reg = 0;
 445         int ret;
 446
 447         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 448         if (ret)
 449                 return -EINVAL;
 450
 451         if (reg >> BOOT_MODE_ALT_SHIFT)
 452                 reg >>= BOOT_MODE_ALT_SHIFT;
 453
 454         bootmode = reg & BOOT_MODES_MASK;
 455
 456         return bootmode;
 457 }
 458
 459 #if defined(CONFIG_BOARD_LATE_INIT)
 460 static const struct {
 461         u32 bit;
 462         const char *name;
 463 } reset_reasons[] = {
 464         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 465         { RESET_REASON_SOFT, "SOFT" },
 466         { RESET_REASON_SRST, "SRST" },
 467         { RESET_REASON_PSONLY, "PS-ONLY" },
 468         { RESET_REASON_PMU, "PMU" },
 469         { RESET_REASON_INTERNAL, "INTERNAL" },
 470         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 471         {}
 472 };
 473
 474 static int reset_reason(void)
 475 {
 476         u32 reg;
 477         int i, ret;
 478         const char *reason = NULL;
 479
 480         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 481         if (ret)
 482                 return -EINVAL;
 483
 484         puts("Reset reason:\t");
 485
 486         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 487                 if (reg & reset_reasons[i].bit) {
 488                         reason = reset_reasons[i].name;
 489                         printf("%s ", reset_reasons[i].name);
 490                         break;
 491                 }
 492         }
 493
 494         puts("\n");
 495
 496         env_set("reset_reason", reason);
 497
 498         ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
 499         if (ret)
 500                 return -EINVAL;
 501
 502         return ret;
 503 }
 504
 505 static int set_fdtfile(void)
 506 {
 507         char *compatible, *fdtfile;
 508         const char *suffix = ".dtb";
 509         const char *vendor = "xilinx/";
 510         int fdt_compat_len;
 511
 512         if (env_get("fdtfile"))
 513                 return 0;
 514
 515         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
 516                                          &fdt_compat_len);
 517         if (compatible && fdt_compat_len) {
 518                 char *name;
 519
 520                 debug("Compatible: %s\n", compatible);
 521
 522                 name = strchr(compatible, ',');
 523                 if (!name)
 524                         return -EINVAL;
 525
 526                 name++;
 527
 528                 fdtfile = calloc(1, strlen(vendor) + strlen(name) +
 529                                  strlen(suffix) + 1);
 530                 if (!fdtfile)
 531                         return -ENOMEM;
 532
 533                 sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
 534
 535                 env_set("fdtfile", fdtfile);
 536                 free(fdtfile);
 537         }
 538
 539         return 0;
 540 }
 541
 542 int board_late_init(void)
 543 {
 544         u8 bootmode;
 545         struct udevice *dev;
 546         int bootseq = -1;
 547         int bootseq_len = 0;
 548         int env_targets_len = 0;
 549         const char *mode;
 550         char *new_targets;
 551         char *env_targets;
 552         int ret;
 553
 554 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 555         usb_ether_init();
 556 #endif
 557
 558         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 559                 debug("Saved variables - Skipping\n");
 560                 return 0;
 561         }
 562
 563         if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
 564                 return 0;
 565
 566         ret = set_fdtfile();
 567         if (ret)
 568                 return ret;
 569
 570         bootmode = zynqmp_get_bootmode();
 571
 572         puts("Bootmode: ");
 573         switch (bootmode) {
 574         case USB_MODE:
 575                 puts("USB_MODE\n");
 576                 mode = "usb";
 577                 env_set("modeboot", "usb_dfu_spl");
 578                 break;
 579         case JTAG_MODE:
 580                 puts("JTAG_MODE\n");
 581                 mode = "jtag pxe dhcp";
 582                 env_set("modeboot", "jtagboot");
 583                 break;
 584         case QSPI_MODE_24BIT:
 585         case QSPI_MODE_32BIT:
 586                 mode = "qspi0";
 587                 puts("QSPI_MODE\n");
 588                 env_set("modeboot", "qspiboot");
 589                 break;
 590         case EMMC_MODE:
 591                 puts("EMMC_MODE\n");
 592                 if (uclass_get_device_by_name(UCLASS_MMC,
 593                                               "mmc@ff160000", &dev) &&
 594                     uclass_get_device_by_name(UCLASS_MMC,
 595                                               "sdhci@ff160000", &dev)) {
 596                         puts("Boot from EMMC but without SD0 enabled!\n");
 597                         return -1;
 598                 }
 599                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 600
 601                 mode = "mmc";
 602                 bootseq = dev->seq;
 603                 break;
 604         case SD_MODE:
 605                 puts("SD_MODE\n");
 606                 if (uclass_get_device_by_name(UCLASS_MMC,
 607                                               "mmc@ff160000", &dev) &&
 608                     uclass_get_device_by_name(UCLASS_MMC,
 609                                               "sdhci@ff160000", &dev)) {
 610                         puts("Boot from SD0 but without SD0 enabled!\n");
 611                         return -1;
 612                 }
 613                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 614
 615                 mode = "mmc";
 616                 bootseq = dev->seq;
 617                 env_set("modeboot", "sdboot");
 618                 break;
 619         case SD1_LSHFT_MODE:
 620                 puts("LVL_SHFT_");
 621                 /* fall through */
 622         case SD_MODE1:
 623                 puts("SD_MODE1\n");
 624                 if (uclass_get_device_by_name(UCLASS_MMC,
 625                                               "mmc@ff170000", &dev) &&
 626                     uclass_get_device_by_name(UCLASS_MMC,
 627                                               "sdhci@ff170000", &dev)) {
 628                         puts("Boot from SD1 but without SD1 enabled!\n");
 629                         return -1;
 630                 }
 631                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 632
 633                 mode = "mmc";
 634                 bootseq = dev->seq;
 635                 env_set("modeboot", "sdboot");
 636                 break;
 637         case NAND_MODE:
 638                 puts("NAND_MODE\n");
 639                 mode = "nand0";
 640                 env_set("modeboot", "nandboot");
 641                 break;
 642         default:
 643                 mode = "";
 644                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 645                 break;
 646         }
 647
 648         if (bootseq >= 0) {
 649                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 650                 debug("Bootseq len: %x\n", bootseq_len);
 651         }
 652
 653         /*
 654          * One terminating char + one byte for space between mode
 655          * and default boot_targets
 656          */
 657         env_targets = env_get("boot_targets");
 658         if (env_targets)
 659                 env_targets_len = strlen(env_targets);
 660
 661         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 662                              bootseq_len);
 663         if (!new_targets)
 664                 return -ENOMEM;
 665
 666         if (bootseq >= 0)
 667                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 668                         env_targets ? env_targets : "");
 669         else
 670                 sprintf(new_targets, "%s %s", mode,
 671                         env_targets ? env_targets : "");
 672
 673         env_set("boot_targets", new_targets);
 674
 675         reset_reason();
 676
 677         return board_late_init_xilinx();
 678 }
 679 #endif
 680
 681 int checkboard(void)
 682 {
 683         puts("Board: Xilinx ZynqMP\n");
 684         return 0;
 685 }
 686
 687 enum env_location env_get_location(enum env_operation op, int prio)
 688 {
 689         u32 bootmode = zynqmp_get_bootmode();
 690
 691         if (prio)
 692                 return ENVL_UNKNOWN;
 693
 694         switch (bootmode) {
 695         case EMMC_MODE:
 696         case SD_MODE:
 697         case SD1_LSHFT_MODE:
 698         case SD_MODE1:
 699                 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
 700                         return ENVL_FAT;
 701                 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
 702                         return ENVL_EXT4;
 703                 return ENVL_UNKNOWN;
 704         case NAND_MODE:
 705                 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
 706                         return ENVL_NAND;
 707                 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
 708                         return ENVL_UBI;
 709                 return ENVL_UNKNOWN;
 710         case QSPI_MODE_24BIT:
 711         case QSPI_MODE_32BIT:
 712                 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
 713                         return ENVL_SPI_FLASH;
 714                 return ENVL_UNKNOWN;
 715         case JTAG_MODE:
 716         default:
 717                 return ENVL_NOWHERE;
 718         }
 719 }